From fdb07713e6d692dddc03a01e5ce7d7458f85fde1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 8 Mar 2018 21:54:26 -0500 Subject: [PATCH] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 Backports commit b96a54c7e5576bd35b7d00d37b7929d2892d8cac from qemu --- qemu/aarch64.h | 2 ++ qemu/aarch64eb.h | 2 ++ qemu/header_gen.py | 1 + qemu/target/arm/helper-a64.c | 11 +++++++++++ qemu/target/arm/helper-a64.h | 2 +- qemu/target/arm/translate-a64.c | 5 +++++ 6 files changed, 22 insertions(+), 1 deletion(-) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 5fe7f893..007325b6 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3770,6 +3770,7 @@ #define helper_crc32_64 helper_crc32_64_aarch64 #define helper_crc32c_64 helper_crc32c_64_aarch64 #define helper_fcvtx_f64_to_f32 helper_fcvtx_f64_to_f32_aarch64 +#define helper_frecpx_f16 helper_frecpx_f16_aarch64 #define helper_frecpx_f32 helper_frecpx_f32_aarch64 #define helper_frecpx_f64 helper_frecpx_f64_aarch64 #define helper_neon_addlp_s16 helper_neon_addlp_s16_aarch64 @@ -3790,6 +3791,7 @@ #define helper_rsqrtsf_f64 helper_rsqrtsf_f64_aarch64 #define helper_sdiv64 helper_sdiv64_aarch64 #define helper_simd_tbl helper_simd_tbl_aarch64 +#define helper_sqrt_f16 helper_sqrt_f16_aarch64 #define helper_udiv64 helper_udiv64_aarch64 #define helper_vfp_cmpd_a64 helper_vfp_cmpd_a64_aarch64 #define helper_vfp_cmped_a64 helper_vfp_cmped_a64_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index c1bea0f6..51851a04 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3770,6 +3770,7 @@ #define helper_crc32_64 helper_crc32_64_aarch64eb #define helper_crc32c_64 helper_crc32c_64_aarch64eb #define helper_fcvtx_f64_to_f32 helper_fcvtx_f64_to_f32_aarch64eb +#define helper_frecpx_f16 helper_frecpx_f16_aarch64eb #define helper_frecpx_f32 helper_frecpx_f32_aarch64eb #define helper_frecpx_f64 helper_frecpx_f64_aarch64eb #define helper_neon_addlp_s16 helper_neon_addlp_s16_aarch64eb @@ -3790,6 +3791,7 @@ #define helper_rsqrtsf_f64 helper_rsqrtsf_f64_aarch64eb #define helper_sdiv64 helper_sdiv64_aarch64eb #define helper_simd_tbl helper_simd_tbl_aarch64eb +#define helper_sqrt_f16 helper_sqrt_f16_aarch64eb #define helper_udiv64 helper_udiv64_aarch64eb #define helper_vfp_cmpd_a64 helper_vfp_cmpd_a64_aarch64eb #define helper_vfp_cmped_a64 helper_vfp_cmped_a64_aarch64eb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 6fa5b88e..de6974fc 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3811,6 +3811,7 @@ aarch64_symbols = ( 'helper_rsqrtsf_f64', 'helper_sdiv64', 'helper_simd_tbl', + 'helper_sqrt_f16', 'helper_udiv64', 'helper_vfp_cmpd_a64', 'helper_vfp_cmped_a64', diff --git a/qemu/target/arm/helper-a64.c b/qemu/target/arm/helper-a64.c index 14bb127c..dcdc3034 100644 --- a/qemu/target/arm/helper-a64.c +++ b/qemu/target/arm/helper-a64.c @@ -874,3 +874,14 @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp) } return float16_to_uint16(a, fpst); } + +/* + * Square Root and Reciprocal square root + */ + +float16 HELPER(sqrt_f16)(float16 a, void *fpstp) +{ + float_status *s = fpstp; + + return float16_sqrt(a, s); +} diff --git a/qemu/target/arm/helper-a64.h b/qemu/target/arm/helper-a64.h index 092423ec..80b8f552 100644 --- a/qemu/target/arm/helper-a64.h +++ b/qemu/target/arm/helper-a64.h @@ -76,4 +76,4 @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) - +DEF_HELPER_2(sqrt_f16, f16, f16, ptr) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 7e5c6d3c..0e2fab21 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -11544,6 +11544,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ need_fpst = false; break; + case 0x7f: /* FSQRT (vector) */ + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); @@ -11657,6 +11659,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_ctx, tcg_res, tcg_op, 0x8000); break; + case 0x7f: /* FSQRT */ + gen_helper_sqrt_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus); + break; default: g_assert_not_reached(); }