From fd4ce2cba0178c184cb889f180c9d43436fbb4e0 Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Thu, 30 Apr 2020 06:53:53 -0400
Subject: [PATCH] target/arm: Assert immh != 0 in disas_simd_shift_imm

Coverity raised a shed-load of errors cascading from inferring
that clz32(immh) might yield 32, from immh might be 0.

While immh cannot be 0 from encoding, it is not obvious even to
a human how we've checked that: via the filtering provided by
data_proc_simd[].

Backports commit 3944d58db3fc5bf131345a21a44013bc13849a12 from qemu
---
 qemu/target/arm/translate-a64.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c
index ff2a5d4d..7d308e41 100644
--- a/qemu/target/arm/translate-a64.c
+++ b/qemu/target/arm/translate-a64.c
@@ -10694,6 +10694,9 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
     bool is_u = extract32(insn, 29, 1);
     bool is_q = extract32(insn, 30, 1);
 
+    /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
+    assert(immh != 0);
+
     switch (opcode) {
     case 0x08: /* SRI */
         if (!is_u) {