From fc8b4316a9cfdcc27e43634686ca470d699d5c66 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 4 Mar 2018 23:39:48 -0500 Subject: [PATCH] tcg: Remove tcg_regset_set32 It's not even clear what the interface REG and VAL32 were supposed to mean. All uses had REG = 0 and VAL32 was the bitset assigned to the destination. Backports commit f46934df662182097dce07d57ec00f37e4d2abf1 from qemu --- qemu/tcg/aarch64/tcg-target.inc.c | 31 +++++++++++---------- qemu/tcg/arm/tcg-target.inc.c | 23 ++++++++-------- qemu/tcg/i386/tcg-target.inc.c | 26 +++++------------ qemu/tcg/mips/tcg-target.inc.c | 35 +++++++++++------------ qemu/tcg/ppc/tcg-target.inc.c | 37 +++++++++++++------------ qemu/tcg/s390/tcg-target.inc.c | 14 +++++----- qemu/tcg/sparc/tcg-target.inc.c | 46 +++++++++++++++---------------- qemu/tcg/tcg.h | 1 - 8 files changed, 102 insertions(+), 111 deletions(-) diff --git a/qemu/tcg/aarch64/tcg-target.inc.c b/qemu/tcg/aarch64/tcg-target.inc.c index ba1736f7..eaa1c5c4 100644 --- a/qemu/tcg/aarch64/tcg-target.inc.c +++ b/qemu/tcg/aarch64/tcg-target.inc.c @@ -125,11 +125,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'r': ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1ULL << TCG_TARGET_NB_REGS) - 1); + ct->u.regs = 0xffffffffu; break; case 'l': /* qemu_ld / qemu_st address, data_reg */ ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1ULL << TCG_TARGET_NB_REGS) - 1); + ct->u.regs = 0xffffffffu; #ifdef CONFIG_SOFTMMU /* x0 and x1 will be overwritten when reading the tlb entry, and x2, and x3 for helper args, better to avoid using them. */ @@ -1940,20 +1940,21 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static void tcg_target_init(TCGContext *s) { - tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); - tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); + s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu; + s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu; - tcg_regset_set32(s->tcg_target_call_clobber_regs, 0, - (1 << TCG_REG_X0) | (1 << TCG_REG_X1) | - (1 << TCG_REG_X2) | (1 << TCG_REG_X3) | - (1 << TCG_REG_X4) | (1 << TCG_REG_X5) | - (1 << TCG_REG_X6) | (1 << TCG_REG_X7) | - (1 << TCG_REG_X8) | (1 << TCG_REG_X9) | - (1 << TCG_REG_X10) | (1 << TCG_REG_X11) | - (1 << TCG_REG_X12) | (1 << TCG_REG_X13) | - (1 << TCG_REG_X14) | (1 << TCG_REG_X15) | - (1 << TCG_REG_X16) | (1 << TCG_REG_X17) | - (1 << TCG_REG_X18) | (1 << TCG_REG_X30)); + s->tcg_target_call_clobber_regs = 0xfffffffu; + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X19); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X20); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X21); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X22); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X23); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X24); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X25); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X26); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X27); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X28); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X29); s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); diff --git a/qemu/tcg/arm/tcg-target.inc.c b/qemu/tcg/arm/tcg-target.inc.c index bc8090f6..05269e08 100644 --- a/qemu/tcg/arm/tcg-target.inc.c +++ b/qemu/tcg/arm/tcg-target.inc.c @@ -264,13 +264,13 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, case 'r': ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); + ct->u.regs = 0xffff; break; /* qemu_ld address */ case 'l': ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); + ct->u.regs = 0xffff; #ifdef CONFIG_SOFTMMU /* r0-r2,lr will be overwritten when reading the tlb entry, so don't use these. */ @@ -284,7 +284,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, /* qemu_st address & data */ case 's': ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); + ct->u.regs = 0xffff; /* r0-r2 will be overwritten when reading the tlb entry (softmmu only) and r0-r1 doing the byte swapping, so don't use these. */ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); @@ -2164,14 +2164,15 @@ static void tcg_target_init(TCGContext *s) } } - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); - tcg_regset_set32(tcg_target_call_clobber_regs, 0, - (1 << TCG_REG_R0) | - (1 << TCG_REG_R1) | - (1 << TCG_REG_R2) | - (1 << TCG_REG_R3) | - (1 << TCG_REG_R12) | - (1 << TCG_REG_R14)); + s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; + + s->tcg_target_call_clobber_regs = 0; + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R0); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R1); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R2); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R3); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R12); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R14); s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); diff --git a/qemu/tcg/i386/tcg-target.inc.c b/qemu/tcg/i386/tcg-target.inc.c index 15868946..6b5a776f 100644 --- a/qemu/tcg/i386/tcg-target.inc.c +++ b/qemu/tcg/i386/tcg-target.inc.c @@ -210,23 +210,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 'q': ct->ct |= TCG_CT_REG; - if (TCG_TARGET_REG_BITS == 64) { - tcg_regset_set32(ct->u.regs, 0, 0xffff); - } else { - tcg_regset_set32(ct->u.regs, 0, 0xf); - } + ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; break; case 'Q': ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xf); + ct->u.regs = 0xf; break; case 'r': ct->ct |= TCG_CT_REG; - if (TCG_TARGET_REG_BITS == 64) { - tcg_regset_set32(ct->u.regs, 0, 0xffff); - } else { - tcg_regset_set32(ct->u.regs, 0, 0xff); - } + ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; break; case 'W': /* With TZCNT/LZCNT, we can have operand-size as an input. */ @@ -236,11 +228,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, /* qemu_ld/st address constraint */ case 'L': ct->ct |= TCG_CT_REG; - if (TCG_TARGET_REG_BITS == 64) { - tcg_regset_set32(ct->u.regs, 0, 0xffff); - } else { - tcg_regset_set32(ct->u.regs, 0, 0xff); - } + ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); break; @@ -2770,10 +2758,10 @@ static void tcg_target_init(TCGContext *s) #endif if (TCG_TARGET_REG_BITS == 64) { - tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); - tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); + s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; + s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; } else { - tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff); + s->tcg_target_available_regs[TCG_TYPE_I32] = 0xff; } s->tcg_target_call_clobber_regs = 0; diff --git a/qemu/tcg/mips/tcg-target.inc.c b/qemu/tcg/mips/tcg-target.inc.c index bf685a4a..17c01953 100644 --- a/qemu/tcg/mips/tcg-target.inc.c +++ b/qemu/tcg/mips/tcg-target.inc.c @@ -2626,23 +2626,24 @@ static void tcg_target_init(TCGContext *s) if (TCG_TARGET_REG_BITS == 64) { s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; } - s->tcg_target_call_clobber_regs = - (1 << TCG_REG_V0) | - (1 << TCG_REG_V1) | - (1 << TCG_REG_A0) | - (1 << TCG_REG_A1) | - (1 << TCG_REG_A2) | - (1 << TCG_REG_A3) | - (1 << TCG_REG_T0) | - (1 << TCG_REG_T1) | - (1 << TCG_REG_T2) | - (1 << TCG_REG_T3) | - (1 << TCG_REG_T4) | - (1 << TCG_REG_T5) | - (1 << TCG_REG_T6) | - (1 << TCG_REG_T7) | - (1 << TCG_REG_T8) | - (1 << TCG_REG_T9); + + s->tcg_target_call_clobber_regs = 0; + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_V0); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_V1); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_A0); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_A1); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_A2); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_A3); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T0); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T1); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T2); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T3); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T4); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T5); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T6); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T7); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T8); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_T9); s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ diff --git a/qemu/tcg/ppc/tcg-target.inc.c b/qemu/tcg/ppc/tcg-target.inc.c index ed5472c7..a96ae55a 100644 --- a/qemu/tcg/ppc/tcg-target.inc.c +++ b/qemu/tcg/ppc/tcg-target.inc.c @@ -277,11 +277,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 'r': ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffffffff); + ct->u.regs = 0xffffffff; break; case 'L': /* qemu_ld constraint */ ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffffffff); + ct->u.regs = 0xffffffff; tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); @@ -290,7 +290,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 'S': /* qemu_st constraint */ ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffffffff); + ct->u.regs = 0xffffffff; tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); @@ -2718,21 +2718,22 @@ static void tcg_target_init(TCGContext *s) } #endif - tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); - tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); - tcg_regset_set32(s->tcg_target_call_clobber_regs, 0, - (1 << TCG_REG_R0) | - (1 << TCG_REG_R2) | - (1 << TCG_REG_R3) | - (1 << TCG_REG_R4) | - (1 << TCG_REG_R5) | - (1 << TCG_REG_R6) | - (1 << TCG_REG_R7) | - (1 << TCG_REG_R8) | - (1 << TCG_REG_R9) | - (1 << TCG_REG_R10) | - (1 << TCG_REG_R11) | - (1 << TCG_REG_R12)); + s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; + s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; + + s->tcg_target_call_clobber_regs = 0; + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R0); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R2); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R3); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R4); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R5); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R6); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R7); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R8); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R9); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R10); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R11); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R12); s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ diff --git a/qemu/tcg/s390/tcg-target.inc.c b/qemu/tcg/s390/tcg-target.inc.c index ef58d7c9..0a512873 100644 --- a/qemu/tcg/s390/tcg-target.inc.c +++ b/qemu/tcg/s390/tcg-target.inc.c @@ -408,14 +408,14 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'r': /* all registers */ ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffff); + ct->u.regs = 0xffff; break; case 'L': /* qemu_ld/st constraint */ ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffff); - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R2); - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); + ct->u.regs = 0xffff; + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); break; case 'a': /* force R2 for division */ ct->ct |= TCG_CT_REG; @@ -2652,8 +2652,8 @@ static void tcg_target_init(TCGContext *s) { query_s390_facilities(); - tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); - tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); + s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; + s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; s->tcg_target_call_clobber_regs = 0; tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R0); diff --git a/qemu/tcg/sparc/tcg-target.inc.c b/qemu/tcg/sparc/tcg-target.inc.c index 7df7b3ff..987bdc45 100644 --- a/qemu/tcg/sparc/tcg-target.inc.c +++ b/qemu/tcg/sparc/tcg-target.inc.c @@ -346,16 +346,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, switch (*ct_str++) { case 'r': ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffffffff); + ct->u.regs = 0xffffffff; break; case 'R': ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, ALL_64); + ct->u.regs = ALL_64; break; case 'A': /* qemu_ld/st address constraint */ ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, - TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff); + ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; reserve_helpers: tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); @@ -363,11 +362,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 's': /* qemu_st data 32-bit constraint */ ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffffffff); + ct->u.regs = 0xffffffff; goto reserve_helpers; case 'S': /* qemu_st data 64-bit constraint */ ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, ALL_64); + ct->u.regs = ALL_64; goto reserve_helpers; case 'I': ct->ct |= TCG_CT_CONST_S11; @@ -1755,24 +1754,25 @@ static void tcg_target_init(TCGContext *s) } #endif - tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); - tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, ALL_64); + s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; + s->tcg_target_available_regs[TCG_TYPE_I64] = ALL_64; - tcg_regset_set32(s->tcg_target_call_clobber_regs, 0, - (1 << TCG_REG_G1) | - (1 << TCG_REG_G2) | - (1 << TCG_REG_G3) | - (1 << TCG_REG_G4) | - (1 << TCG_REG_G5) | - (1 << TCG_REG_G6) | - (1 << TCG_REG_G7) | - (1 << TCG_REG_O0) | - (1 << TCG_REG_O1) | - (1 << TCG_REG_O2) | - (1 << TCG_REG_O3) | - (1 << TCG_REG_O4) | - (1 << TCG_REG_O5) | - (1 << TCG_REG_O7)); + s->tcg_target_call_clobber_regs = 0; + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G1); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G2); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G3); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G4); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G5); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G6); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_G7); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O0); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O1); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O2); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O3); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O4); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O5); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O6); + tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_O7); s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h index 157d25a7..4fb90cf2 100644 --- a/qemu/tcg/tcg.h +++ b/qemu/tcg/tcg.h @@ -189,7 +189,6 @@ typedef enum TCGOpcode { NB_OPS, } TCGOpcode; -#define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg) #define tcg_regset_set_reg(d, r) (d) |= 1L << (r) #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r)) #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)