From f893ff0b896abdef2e6a4a493314a16aaca33ad1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 8 Aug 2019 19:28:32 -0400 Subject: [PATCH] target/arm: report ARMv8-A FP support for AArch32 -cpu max When we converted to using feature bits in 602f6e42cfbf we missed out the fact (dp && arm_dc_feature(s, ARM_FEATURE_V8)) was supported for -cpu max configurations. This caused a regression in the GCC test suite. Fix this by setting the appropriate bits in mvfr1.FPHP to report ARMv8-A with FP support (but not ARMv8.2-FP16). Fixes: https://bugs.launchpad.net/qemu/+bug/1836078 Backports commit 45b1a243b81a7c9ae56235937280711dd9914ca7 from qemu --- qemu/target/arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index a47950c8..531b98f3 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -1745,6 +1745,10 @@ static void arm_max_initfn(struct uc_struct *uc, Object *obj, void *opaque) t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 = t; + t = cpu->isar.mvfr1; + t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ + cpu->isar.mvfr1 = t; + t = cpu->isar.mvfr2; t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */