From f5b3b9f6e9a61a7abb6039418fe482d5ef4d94b3 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Thu, 15 Feb 2018 12:33:38 -0500 Subject: [PATCH] target-arm: Suppress TBI for S2 translations Stage-2 MMU translations do not have configurable TBI as the top byte is always 0 (48-bit IPAs). Backports commit 1edee4708a0e3163cbf20fac325be456abd960bb from qemu --- qemu/target-arm/helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index 7e72af2a..c0881731 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -5743,7 +5743,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (arm_el_is_aa64(env, el)) { va_size = 64; if (el > 1) { - tbi = extract64(tcr->raw_tcr, 20, 1); + if (mmu_idx != ARMMMUIdx_S2NS) { + tbi = extract64(tcr->raw_tcr, 20, 1); + } } else { if (extract64(address, 55, 1)) { tbi = extract64(tcr->raw_tcr, 38, 1);