diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 6526e065..5808047d 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_aarch64 #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_aarch64 #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_aarch64 +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_aarch64 +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_aarch64 #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_aarch64 #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_aarch64 #define tcg_gen_nand_i32 tcg_gen_nand_i32_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 79a8a920..dd5e3271 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_aarch64eb #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_aarch64eb #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_aarch64eb +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_aarch64eb +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_aarch64eb #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_aarch64eb #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_aarch64eb #define tcg_gen_nand_i32 tcg_gen_nand_i32_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index 1fda8929..fc680d7b 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_arm #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_arm #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_arm +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_arm +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_arm #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_arm #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_arm #define tcg_gen_nand_i32 tcg_gen_nand_i32_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index d9a08f05..8adc1579 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_armeb #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_armeb #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_armeb +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_armeb +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_armeb #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_armeb #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_armeb #define tcg_gen_nand_i32 tcg_gen_nand_i32_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 66e0ce55..6910adbd 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3020,6 +3020,8 @@ symbols = ( 'tcg_gen_muli_i64', 'tcg_gen_muls2_i32', 'tcg_gen_muls2_i64', + 'tcg_gen_mulsu2_i32', + 'tcg_gen_mulsu2_i64', 'tcg_gen_mulu2_i32', 'tcg_gen_mulu2_i64', 'tcg_gen_nand_i32', diff --git a/qemu/m68k.h b/qemu/m68k.h index c46da1d7..ad2f8478 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_m68k #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_m68k #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_m68k +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_m68k +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_m68k #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_m68k #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_m68k #define tcg_gen_nand_i32 tcg_gen_nand_i32_m68k diff --git a/qemu/mips.h b/qemu/mips.h index a3a9c13b..c6b9b1c0 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_mips #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_mips +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_mips #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips #define tcg_gen_nand_i32 tcg_gen_nand_i32_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index 91fefdce..26b1a2c3 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_mips64 #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips64 #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips64 +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_mips64 +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_mips64 #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips64 #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips64 #define tcg_gen_nand_i32 tcg_gen_nand_i32_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 2cf5f04e..5bd22bad 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_mips64el #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips64el #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips64el +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_mips64el +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_mips64el #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips64el #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips64el #define tcg_gen_nand_i32 tcg_gen_nand_i32_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 005074d0..ddde00b3 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_mipsel #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mipsel #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mipsel +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_mipsel +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_mipsel #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mipsel #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mipsel #define tcg_gen_nand_i32 tcg_gen_nand_i32_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index 88b8ec8b..c4f49f0b 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_powerpc #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_powerpc #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_powerpc +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_powerpc +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_powerpc #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_powerpc #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_powerpc #define tcg_gen_nand_i32 tcg_gen_nand_i32_powerpc diff --git a/qemu/sparc.h b/qemu/sparc.h index e192c7ae..a60ccd41 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_sparc #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_sparc #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_sparc +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_sparc +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_sparc #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_sparc #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_sparc #define tcg_gen_nand_i32 tcg_gen_nand_i32_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index 62cf3d59..e37176ca 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_sparc64 #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_sparc64 #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_sparc64 +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_sparc64 +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_sparc64 #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_sparc64 #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_sparc64 #define tcg_gen_nand_i32 tcg_gen_nand_i32_sparc64 diff --git a/qemu/tcg/tcg-op.c b/qemu/tcg/tcg-op.c index 374a485e..81ab5b3b 100644 --- a/qemu/tcg/tcg-op.c +++ b/qemu/tcg/tcg-op.c @@ -677,6 +677,33 @@ void tcg_gen_muls2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, T } } +void tcg_gen_mulsu2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_REG_BITS == 32) { + TCGv_i32 t0 = tcg_temp_new_i32(s); + TCGv_i32 t1 = tcg_temp_new_i32(s); + TCGv_i32 t2 = tcg_temp_new_i32(s); + tcg_gen_mulu2_i32(s, t0, t1, arg1, arg2); + /* Adjust for negative input for the signed arg1. */ + tcg_gen_sari_i32(s, t2, arg1, 31); + tcg_gen_and_i32(s, t2, t2, arg2); + tcg_gen_sub_i32(s, rh, t1, t2); + tcg_gen_mov_i32(s, rl, t0); + tcg_temp_free_i32(s, t0); + tcg_temp_free_i32(s, t1); + tcg_temp_free_i32(s, t2); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(s); + TCGv_i64 t1 = tcg_temp_new_i64(s); + tcg_gen_ext_i32_i64(s, t0, arg1); + tcg_gen_extu_i32_i64(s, t1, arg2); + tcg_gen_mul_i64(s, t0, t0, t1); + tcg_gen_extr_i64_i32(s, rl, rh, t0); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + } +} + void tcg_gen_ext8s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg) { if (TCG_TARGET_HAS_ext8s_i32) { @@ -1747,6 +1774,22 @@ void tcg_gen_muls2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, T } } +void tcg_gen_mulsu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) +{ + TCGv_i64 t0 = tcg_temp_new_i64(s); + TCGv_i64 t1 = tcg_temp_new_i64(s); + TCGv_i64 t2 = tcg_temp_new_i64(s); + tcg_gen_mulu2_i64(s, t0, t1, arg1, arg2); + /* Adjust for negative input for the signed arg1. */ + tcg_gen_sari_i64(s, t2, arg1, 63); + tcg_gen_and_i64(s, t2, t2, arg2); + tcg_gen_sub_i64(s, rh, t1, t2); + tcg_gen_mov_i64(s, rl, t0); + tcg_temp_free_i64(s, t0); + tcg_temp_free_i64(s, t1); + tcg_temp_free_i64(s, t2); +} + /* Size changing operations. */ void tcg_gen_extrl_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg) diff --git a/qemu/tcg/tcg-op.h b/qemu/tcg/tcg-op.h index cb46da05..33efd231 100644 --- a/qemu/tcg/tcg-op.h +++ b/qemu/tcg/tcg-op.h @@ -314,6 +314,7 @@ void tcg_gen_sub2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); void tcg_gen_mulu2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_muls2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_mulsu2_i32(TCGContext *s, TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_ext8s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext16s_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext8u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); @@ -482,6 +483,7 @@ void tcg_gen_sub2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); void tcg_gen_mulu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_muls2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_mulsu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_not_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext8s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_ext16s_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); @@ -958,6 +960,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg #define tcg_gen_sub2_tl tcg_gen_sub2_i64 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 #define tcg_gen_muls2_tl tcg_gen_muls2_i64 +#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 @@ -1045,6 +1048,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg #define tcg_gen_sub2_tl tcg_gen_sub2_i32 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 #define tcg_gen_muls2_tl tcg_gen_muls2_i32 +#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 diff --git a/qemu/x86_64.h b/qemu/x86_64.h index 3d8e66d7..3654cd5e 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -3014,6 +3014,8 @@ #define tcg_gen_muli_i64 tcg_gen_muli_i64_x86_64 #define tcg_gen_muls2_i32 tcg_gen_muls2_i32_x86_64 #define tcg_gen_muls2_i64 tcg_gen_muls2_i64_x86_64 +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_x86_64 +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_x86_64 #define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_x86_64 #define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_x86_64 #define tcg_gen_nand_i32 tcg_gen_nand_i32_x86_64