From f425b6aa813e43552fe5bb8c86d5af2bcdc35dcb Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Wed, 7 Mar 2018 08:58:39 -0500 Subject: [PATCH] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to AArch64 user mode emulation. Backports commit 955f56d44a73d74016b2e71765d984ac7a6db1dc from qemu --- qemu/target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qemu/target/arm/cpu64.c b/qemu/target/arm/cpu64.c index ccaf1b14..25e37abf 100644 --- a/qemu/target/arm/cpu64.c +++ b/qemu/target/arm/cpu64.c @@ -202,6 +202,10 @@ static void aarch64_any_initfn(struct uc_struct *uc, Object *obj, void *opaque) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ }