From f0ed9c807cd6fcb8a9c976bd124d4bffb77a0041 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 12 Feb 2018 22:20:34 -0500 Subject: [PATCH] target-arm: Set correct syndrome for faults on MSR DAIF*, imm If the SCTLR.UMA trap bit is set then attempts by EL0 to update the PSTATE DAIF bits via "MSR DAIFSet, imm" and "MSR DAIFClr, imm" instructions will raise an exception. We were failing to set the syndrome information for this exception, which meant that it would be reported as a repeat of whatever the previous exception was. Set the correct syndrome information. Backports commit f2932df777dace044719dc2f394f5a5a8aa1b1cd from qemu --- qemu/target-arm/op_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qemu/target-arm/op_helper.c b/qemu/target-arm/op_helper.c index 190b422c..e614f3ba 100644 --- a/qemu/target-arm/op_helper.c +++ b/qemu/target-arm/op_helper.c @@ -381,6 +381,9 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) */ if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { env->exception.target_el = exception_target_el(env); + env->exception.syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3), + extract32(op, 3, 3), 4, + imm, 0x1f, 0); raise_exception(env, EXCP_UDEF); }