From eb4796e96565de302c1a885d8a4a7e58beddfd84 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 8 Mar 2018 23:00:53 -0500 Subject: [PATCH] target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 any CPU Now we have implemented FP16 we can enable it for the "any" CPU. Backports commit 969b389ee8ba84bc3f2e7ccfa993679fac410ad2 from qemu --- qemu/target/arm/cpu64.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/cpu64.c b/qemu/target/arm/cpu64.c index 25e37abf..21efc1ae 100644 --- a/qemu/target/arm/cpu64.c +++ b/qemu/target/arm/cpu64.c @@ -200,12 +200,13 @@ static void aarch64_any_initfn(struct uc_struct *uc, Object *obj, void *opaque) set_feature(&cpu->env, ARM_FEATURE_V8_AES); set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); - set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); set_feature(&cpu->env, ARM_FEATURE_V8_SM3); set_feature(&cpu->env, ARM_FEATURE_V8_SM4); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ }