From eaecbe7901196c0782db3d4e22cd2ebf675866ca Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 3 Feb 2019 17:39:51 -0500 Subject: [PATCH] target/arm/translate-a64: Don't underdecode SDOT and UDOT In the AdvSIMD scalar x indexed element and vector x indexed element encoding group, the SDOT and UDOT instructions are vector only, and their opcode is unallocated in the scalar group. Correctly UNDEF this unallocated encoding. Backports commit 4977986ca38fb1d5357532e1a8032b984047a369 from qemu --- qemu/target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 50671723..15bb540c 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -12812,7 +12812,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) break; case 0x0e: /* SDOT */ case 0x1e: /* UDOT */ - if (size != MO_32 || !dc_isar_feature(aa64_dp, s)) { + if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_dp, s)) { unallocated_encoding(s); return; }