From e74588a57f0205daa69ebc88e1cd6c41ac669b32 Mon Sep 17 00:00:00 2001 From: Georg Kotheimer Date: Tue, 30 Mar 2021 15:14:11 -0400 Subject: [PATCH] target/riscv: Use background registers also for MSTATUS_MPV The current condition for the use of background registers only considers the hypervisor load and store instructions, but not accesses from M mode via MSTATUS_MPRV+MPV. Backports db9ab38b81058b41e5f469165067feea46762eee --- qemu/target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target/riscv/cpu_helper.c b/qemu/target/riscv/cpu_helper.c index 8b87ea26..1a969656 100644 --- a/qemu/target/riscv/cpu_helper.c +++ b/qemu/target/riscv/cpu_helper.c @@ -357,7 +357,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ - if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) { + if (!riscv_cpu_virt_enabled(env) && two_stage) { use_background = true; }