From e6eb25f75a972710836662a6ba57613ed0c4adb0 Mon Sep 17 00:00:00 2001 From: Leif Lindholm Date: Wed, 3 Mar 2021 20:12:46 -0500 Subject: [PATCH] target/arm: make ARMCPU.clidr 64-bit The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit 32, as well as adding a Ttype field when FEAT_MTE is implemented. Extend the clidr field to be able to hold this context. Backports f6450bcb6b2d3e4beae77141edce9e99cb8c277e --- qemu/target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index 743ccd66..72b7e956 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -891,7 +891,7 @@ struct ARMCPU { uint32_t id_afr0; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint32_t clidr; + uint64_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.