From e63f70f980a69d5c403fe0da9e3b357d9d813d30 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sat, 21 Mar 2020 18:07:48 -0400 Subject: [PATCH] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers Enforce a convention that an isar_feature function that tests a 32-bit ID register always has _aa32_ in its name, and one that tests a 64-bit ID register always has _aa64_ in its name. We already follow this except for three cases: thumb_div, arm_div and jazelle, which all need _aa32_ adding. (As noted in the comment, isar_feature_aa32_fp16_arith() is an exception in that it currently tests ID_AA64PFR0_EL1, but will switch to MVFR1 once we've properly implemented FP16 for AArch32.) Backports commit 873b73c0c891ec20adacc7bd1ae789294334d675 from qemu --- qemu/target/arm/cpu.c | 6 ++++-- qemu/target/arm/cpu.h | 6 +++--- qemu/target/arm/helper.c | 2 +- qemu/target/arm/internals.h | 2 +- qemu/target/arm/translate.c | 6 +++--- 5 files changed, 12 insertions(+), 10 deletions(-) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index 9f958a28..1d8b865b 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -844,7 +844,8 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err * Presence of EL2 itself is ARM_FEATURE_EL2, and of the * Security Extensions is ARM_FEATURE_EL3. */ - assert(!tcg_enabled(uc) || no_aa32 || cpu_isar_feature(arm_div, cpu)); + assert(!tcg_enabled(uc) || no_aa32 || + cpu_isar_feature(aa32_arm_div, cpu)); set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_V7); } @@ -870,7 +871,8 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); if (!arm_feature(env, ARM_FEATURE_M)) { - assert(!tcg_enabled(uc) || no_aa32 || cpu_isar_feature(jazelle, cpu)); + assert(!tcg_enabled(uc) || no_aa32 || + cpu_isar_feature(aa32_jazelle, cpu)); set_feature(env, ARM_FEATURE_AUXCR); } } diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index c95e62c6..6cd29b57 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -3200,17 +3200,17 @@ extern const uint64_t pred_esz_masks[4]; /* * 32-bit feature tests via id registers. */ -static inline bool isar_feature_thumb_div(const ARMISARegisters *id) +static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; } -static inline bool isar_feature_arm_div(const ARMISARegisters *id) +static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; } -static inline bool isar_feature_jazelle(const ARMISARegisters *id) +static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; } diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 16ecbc0b..7465344b 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -7180,7 +7180,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, lpae_cp_reginfo); } - if (cpu_isar_feature(jazelle, cpu)) { + if (cpu_isar_feature(aa32_jazelle, cpu)) { define_arm_cp_regs(cpu, jazelle_regs); } /* Slightly awkwardly, the OMAP and StrongARM cores need all of diff --git a/qemu/target/arm/internals.h b/qemu/target/arm/internals.h index 995e20a6..bd386e85 100644 --- a/qemu/target/arm/internals.h +++ b/qemu/target/arm/internals.h @@ -1093,7 +1093,7 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, if ((features >> ARM_FEATURE_THUMB2) & 1) { valid |= CPSR_IT; } - if (isar_feature_jazelle(id)) { + if (isar_feature_aa32_jazelle(id)) { valid |= CPSR_J; } if (isar_feature_aa32_pan(id)) { diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index bf188fa9..cf240295 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -41,7 +41,7 @@ #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) -#define ENABLE_ARCH_5J dc_isar_feature(jazelle, s) +#define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s) #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) @@ -10139,8 +10139,8 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool u) TCGv_i32 t1, t2; if (s->thumb - ? !dc_isar_feature(thumb_div, s) - : !dc_isar_feature(arm_div, s)) { + ? !dc_isar_feature(aa32_thumb_div, s) + : !dc_isar_feature(aa32_arm_div, s)) { return false; }