diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c
index b9adde78..d66c63d7 100644
--- a/qemu/target/arm/cpu.c
+++ b/qemu/target/arm/cpu.c
@@ -593,7 +593,11 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
 
     /* Some features automatically imply others: */
     if (arm_feature(env, ARM_FEATURE_V8)) {
-        set_feature(env, ARM_FEATURE_V7VE);
+        if (arm_feature(env, ARM_FEATURE_M)) {
+            set_feature(env, ARM_FEATURE_V7);
+        } else {
+            set_feature(env, ARM_FEATURE_V7VE);
+        }
     }
     if (arm_feature(env, ARM_FEATURE_V7VE)) {
         /* v7 Virtualization Extensions. In real hardware this implies
diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c
index cbdb4b86..bbcf498e 100644
--- a/qemu/target/arm/helper.c
+++ b/qemu/target/arm/helper.c
@@ -4400,7 +4400,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
              * define these regs.
              */
             { "ID_AA64PFR0_EL1", 0,0,4, 3,0,0, ARM_CP_STATE_AA64,
-              ARM_CP_NO_RAW, PL1_R, 0, NULL, cpu->id_aa64pfr0, 0, {0, 0},
+              ARM_CP_NO_RAW, PL1_R, 0, NULL, cpu->isar.id_aa64pfr0, 0, {0, 0},
               NULL, id_aa64pfr0_read, arm_cp_write_ignore },
             { "ID_AA64PFR1_EL1", 0,0,4, 3,0,1, ARM_CP_STATE_AA64,
               ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_aa64pfr1},