From e3f1f25996d545c7b8a7e4f6db382346d430cd89 Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Wed, 12 Jun 2019 11:06:27 -0400
Subject: [PATCH] cpu: Define CPUArchState with typedef

For all targets, do this just before including exec/cpu-all.h.

Backports commit 4f7c64b3819d559417615ed2b1d028ebc1a49580 from qemu
---
 qemu/target/arm/cpu.h   | 4 ++--
 qemu/target/i386/cpu.h  | 4 ++--
 qemu/target/m68k/cpu.h  | 4 ++--
 qemu/target/mips/cpu.h  | 6 ++----
 qemu/target/riscv/cpu.h | 4 ++--
 qemu/target/sparc/cpu.h | 4 ++--
 6 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h
index 4567b32e..7b3ef787 100644
--- a/qemu/target/arm/cpu.h
+++ b/qemu/target/arm/cpu.h
@@ -31,8 +31,6 @@
 /* ARM processors have a weak memory model */
 #define TCG_GUEST_DEFAULT_MO      (0)
 
-#define CPUArchState struct CPUARMState
-
 #define EXCP_UDEF            1   /* undefined instruction */
 #define EXCP_SWI             2   /* software interrupt */
 #define EXCP_PREFETCH_ABORT  3
@@ -3081,6 +3079,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
     }
 }
 
+typedef CPUARMState CPUArchState;
+
 #include "exec/cpu-all.h"
 
 /* Bit usage in the TB flags field: bit 31 indicates whether we are
diff --git a/qemu/target/i386/cpu.h b/qemu/target/i386/cpu.h
index 15c2d160..c84575ea 100644
--- a/qemu/target/i386/cpu.h
+++ b/qemu/target/i386/cpu.h
@@ -42,8 +42,6 @@
 #define ELF_MACHINE_UNAME "i686"
 #endif
 
-#define CPUArchState struct CPUX86State
-
 #include "exec/cpu-defs.h"
 
 #define R_EAX 0
@@ -1672,6 +1670,8 @@ static inline target_long lshift(target_long x, int n)
 /* translate.c */
 void tcg_x86_init(struct uc_struct *);
 
+typedef CPUX86State CPUArchState;
+
 #include "exec/cpu-all.h"
 #include "svm.h"
 
diff --git a/qemu/target/m68k/cpu.h b/qemu/target/m68k/cpu.h
index 62df92bc..e7396b30 100644
--- a/qemu/target/m68k/cpu.h
+++ b/qemu/target/m68k/cpu.h
@@ -26,8 +26,6 @@
 #include "cpu-qom.h"
 #include "exec/cpu-defs.h"
 
-#define CPUArchState struct CPUM68KState
-
 #define OS_BYTE     0
 #define OS_WORD     1
 #define OS_LONG     2
@@ -533,6 +531,8 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
                                  int mmu_idx, MemTxAttrs attrs,
                                  MemTxResult response, uintptr_t retaddr);
 
+typedef CPUM68KState CPUArchState;
+
 #include "exec/cpu-all.h"
 
 /* TB flags */
diff --git a/qemu/target/mips/cpu.h b/qemu/target/mips/cpu.h
index 164f6534..dd42f5be 100644
--- a/qemu/target/mips/cpu.h
+++ b/qemu/target/mips/cpu.h
@@ -3,8 +3,6 @@
 
 #define ALIGNED_ONLY
 
-#define CPUArchState struct CPUMIPSState
-
 #include "config.h"
 #include "qemu-common.h"
 #include "cpu-qom.h"
@@ -12,8 +10,6 @@
 #include "fpu/softfloat.h"
 #include "mips-defs.h"
 
-struct CPUMIPSState;
-
 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
 
 /* MSA Context */
@@ -1116,6 +1112,8 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
     return hflags_mmu_index(env->hflags);
 }
 
+typedef CPUMIPSState CPUArchState;
+
 #include "exec/cpu-all.h"
 
 /*
diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h
index 9353599d..a8e1726f 100644
--- a/qemu/target/riscv/cpu.h
+++ b/qemu/target/riscv/cpu.h
@@ -92,8 +92,6 @@ enum {
 
 #define MAX_RISCV_PMPS (16)
 
-typedef struct CPURISCVState CPURISCVState;
-
 #include "pmp.h"
 
 struct CPURISCVState {
@@ -331,6 +329,8 @@ typedef struct {
 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
+typedef CPURISCVState CPUArchState;
+
 #include "exec/cpu-all.h"
 
 // Unicorn-specific
diff --git a/qemu/target/sparc/cpu.h b/qemu/target/sparc/cpu.h
index 71c1aaa9..64e185fa 100644
--- a/qemu/target/sparc/cpu.h
+++ b/qemu/target/sparc/cpu.h
@@ -14,8 +14,6 @@
 #define TARGET_DPREGS 32
 #endif
 
-#define CPUArchState struct CPUSPARCState
-
 /*#define EXCP_INTERRUPT 0x100*/
 
 /* trap definitions */
@@ -720,6 +718,8 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
 #endif
 }
 
+typedef CPUSPARCState CPUArchState;
+
 #include "exec/cpu-all.h"
 
 #ifdef TARGET_SPARC64