From e3ea2c039366594aa512f0c1d82b684764cb5f6d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Llu=C3=ADs=20Vilanova?= Date: Sun, 4 Mar 2018 17:16:52 -0500 Subject: [PATCH] target/i386: [tcg] Port to breakpoint_check Incrementally paves the way towards using the generic instruction translation loop. Backports commit e6b41ec37f0a9742374dfdb90e662745969cd7ea from qemu --- qemu/target/i386/translate.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/qemu/target/i386/translate.c b/qemu/target/i386/translate.c index 2d62f906..8c4a2f78 100644 --- a/qemu/target/i386/translate.c +++ b/qemu/target/i386/translate.c @@ -9233,6 +9233,26 @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(tcg_ctx, dc->base.pc_next, dc->cc_op); } +static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + /* If RF is set, suppress an internally generated breakpoint. */ + int flags = dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; + if (bp->flags & flags) { + gen_debug(dc, dc->base.pc_next - dc->cs_base); + dc->base.is_jmp = DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next += 1; + return true; + } else { + return false; + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) {