diff --git a/qemu/aarch64.h b/qemu/aarch64.h
index 21300719..ea952201 100644
--- a/qemu/aarch64.h
+++ b/qemu/aarch64.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_aarch64
 #define ti925t_initfn ti925t_initfn_aarch64
 #define tlb_add_large_page tlb_add_large_page_aarch64
+#define tlb_init tlb_init_aarch64
 #define tlb_fill tlb_fill_aarch64
 #define tlb_flush tlb_flush_aarch64
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64
diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h
index 04ba3974..929224e0 100644
--- a/qemu/aarch64eb.h
+++ b/qemu/aarch64eb.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_aarch64eb
 #define ti925t_initfn ti925t_initfn_aarch64eb
 #define tlb_add_large_page tlb_add_large_page_aarch64eb
+#define tlb_init tlb_init_aarch64eb
 #define tlb_fill tlb_fill_aarch64eb
 #define tlb_flush tlb_flush_aarch64eb
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64eb
diff --git a/qemu/accel/tcg/cputlb.c b/qemu/accel/tcg/cputlb.c
index ca6813bb..a1e08529 100644
--- a/qemu/accel/tcg/cputlb.c
+++ b/qemu/accel/tcg/cputlb.c
@@ -66,6 +66,10 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
                                target_ulong size);
 static void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr);
 
+void tlb_init(CPUState *cpu)
+{
+}
+
 /* This is OK because CPU architectures generally permit an
  * implementation to drop entries from the TLB at any time, so
  * flushing more entries than required is only an efficiency issue,
diff --git a/qemu/arm.h b/qemu/arm.h
index 08683eb3..66f39efc 100644
--- a/qemu/arm.h
+++ b/qemu/arm.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_arm
 #define ti925t_initfn ti925t_initfn_arm
 #define tlb_add_large_page tlb_add_large_page_arm
+#define tlb_init tlb_init_arm
 #define tlb_fill tlb_fill_arm
 #define tlb_flush tlb_flush_arm
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_arm
diff --git a/qemu/armeb.h b/qemu/armeb.h
index c8ad828f..f3ff189f 100644
--- a/qemu/armeb.h
+++ b/qemu/armeb.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_armeb
 #define ti925t_initfn ti925t_initfn_armeb
 #define tlb_add_large_page tlb_add_large_page_armeb
+#define tlb_init tlb_init_armeb
 #define tlb_fill tlb_fill_armeb
 #define tlb_flush tlb_flush_armeb
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_armeb
diff --git a/qemu/exec.c b/qemu/exec.c
index 36231b40..5fab748d 100644
--- a/qemu/exec.c
+++ b/qemu/exec.c
@@ -644,6 +644,7 @@ void cpu_exec_init(CPUState *cpu, Error **errp, void *opaque)
         cc->tcg_initialized = true;
         cc->tcg_initialize(uc);
     }
+    tlb_init(cpu);
 
 #ifndef CONFIG_USER_ONLY
 
diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index f08d6fbc..48be9fd1 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -3129,6 +3129,7 @@ symbols = (
     'thumb2_logic_op',
     'ti925t_initfn',
     'tlb_add_large_page',
+    'tlb_init',
     'tlb_fill',
     'tlb_flush',
     'tlb_flush_by_mmuidx',
diff --git a/qemu/include/exec/exec-all.h b/qemu/include/exec/exec-all.h
index 8ad51153..8cf76775 100644
--- a/qemu/include/exec/exec-all.h
+++ b/qemu/include/exec/exec-all.h
@@ -109,6 +109,11 @@ void cpu_address_space_init(CPUState *cpu, int asidx,
 
 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
 /* cputlb.c */
+/**
+ * tlb_init - initialize a CPU's TLB
+ * @cpu: CPU whose TLB should be initialized
+ */
+void tlb_init(CPUState *cpu);
 /**
  * tlb_flush_page:
  * @cpu: CPU whose TLB should be flushed
diff --git a/qemu/m68k.h b/qemu/m68k.h
index 2513dc91..77bd1dcb 100644
--- a/qemu/m68k.h
+++ b/qemu/m68k.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_m68k
 #define ti925t_initfn ti925t_initfn_m68k
 #define tlb_add_large_page tlb_add_large_page_m68k
+#define tlb_init tlb_init_m68k
 #define tlb_fill tlb_fill_m68k
 #define tlb_flush tlb_flush_m68k
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_m68k
diff --git a/qemu/mips.h b/qemu/mips.h
index af1f9d70..e8a9dcce 100644
--- a/qemu/mips.h
+++ b/qemu/mips.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_mips
 #define ti925t_initfn ti925t_initfn_mips
 #define tlb_add_large_page tlb_add_large_page_mips
+#define tlb_init tlb_init_mips
 #define tlb_fill tlb_fill_mips
 #define tlb_flush tlb_flush_mips
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips
diff --git a/qemu/mips64.h b/qemu/mips64.h
index cbb71d61..d8e12d35 100644
--- a/qemu/mips64.h
+++ b/qemu/mips64.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_mips64
 #define ti925t_initfn ti925t_initfn_mips64
 #define tlb_add_large_page tlb_add_large_page_mips64
+#define tlb_init tlb_init_mips64
 #define tlb_fill tlb_fill_mips64
 #define tlb_flush tlb_flush_mips64
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64
diff --git a/qemu/mips64el.h b/qemu/mips64el.h
index 5bfc3ee2..7acba030 100644
--- a/qemu/mips64el.h
+++ b/qemu/mips64el.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_mips64el
 #define ti925t_initfn ti925t_initfn_mips64el
 #define tlb_add_large_page tlb_add_large_page_mips64el
+#define tlb_init tlb_init_mips64el
 #define tlb_fill tlb_fill_mips64el
 #define tlb_flush tlb_flush_mips64el
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64el
diff --git a/qemu/mipsel.h b/qemu/mipsel.h
index b5b56c1a..ec1b7af9 100644
--- a/qemu/mipsel.h
+++ b/qemu/mipsel.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_mipsel
 #define ti925t_initfn ti925t_initfn_mipsel
 #define tlb_add_large_page tlb_add_large_page_mipsel
+#define tlb_init tlb_init_mipsel
 #define tlb_fill tlb_fill_mipsel
 #define tlb_flush tlb_flush_mipsel
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mipsel
diff --git a/qemu/powerpc.h b/qemu/powerpc.h
index 85be0364..e1d74e07 100644
--- a/qemu/powerpc.h
+++ b/qemu/powerpc.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_powerpc
 #define ti925t_initfn ti925t_initfn_powerpc
 #define tlb_add_large_page tlb_add_large_page_powerpc
+#define tlb_init tlb_init_powerpc
 #define tlb_fill tlb_fill_powerpc
 #define tlb_flush tlb_flush_powerpc
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_powerpc
diff --git a/qemu/sparc.h b/qemu/sparc.h
index b9d2b7b6..cc85b0f2 100644
--- a/qemu/sparc.h
+++ b/qemu/sparc.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_sparc
 #define ti925t_initfn ti925t_initfn_sparc
 #define tlb_add_large_page tlb_add_large_page_sparc
+#define tlb_init tlb_init_sparc
 #define tlb_fill tlb_fill_sparc
 #define tlb_flush tlb_flush_sparc
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc
diff --git a/qemu/sparc64.h b/qemu/sparc64.h
index 09c7f480..803d3877 100644
--- a/qemu/sparc64.h
+++ b/qemu/sparc64.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_sparc64
 #define ti925t_initfn ti925t_initfn_sparc64
 #define tlb_add_large_page tlb_add_large_page_sparc64
+#define tlb_init tlb_init_sparc64
 #define tlb_fill tlb_fill_sparc64
 #define tlb_flush tlb_flush_sparc64
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc64
diff --git a/qemu/x86_64.h b/qemu/x86_64.h
index 10bfcd3b..9b10e25b 100644
--- a/qemu/x86_64.h
+++ b/qemu/x86_64.h
@@ -3123,6 +3123,7 @@
 #define thumb2_logic_op thumb2_logic_op_x86_64
 #define ti925t_initfn ti925t_initfn_x86_64
 #define tlb_add_large_page tlb_add_large_page_x86_64
+#define tlb_init tlb_init_x86_64
 #define tlb_fill tlb_fill_x86_64
 #define tlb_flush tlb_flush_x86_64
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_x86_64