From dbeb82e4241a6efc0256cbd69166994937427e2d Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Fri, 25 Jan 2019 12:46:45 -0500 Subject: [PATCH] target/mips: Extend gen_scwp() functionality to support EVA Extend gen_scwp() functionality to support EVA by adding an additional argument, modify internals of the function to handle new functionality, and accordingly change its invocations. Backports commit 8d5388c1de8bf207316369213bd950bafa6badda from qemu --- qemu/target/mips/translate.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index 32da5ebd..7abf29cb 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -3729,7 +3729,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, } static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, - uint32_t reg1, uint32_t reg2) + uint32_t reg1, uint32_t reg2, bool eva) { TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGv taddr = tcg_temp_local_new(tcg_ctx); @@ -3758,7 +3758,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, tcg_gen_ld_i64(tcg_ctx, llval, tcg_ctx->cpu_env, offsetof(CPUMIPSState, llval_wp)); tcg_gen_atomic_cmpxchg_i64(tcg_ctx, val, taddr, llval, tval, - ctx->mem_idx, MO_64); + eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64); if (reg1 != 0) { tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[reg1], 1); } @@ -21683,7 +21683,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) break; case NM_SCWP: check_xnp(ctx); - gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5)); + gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5), + false); break; } break; @@ -21787,7 +21788,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) check_xnp(ctx); check_eva(ctx); check_cp0_enabled(ctx); - gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5)); + gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5), + true); break; default: generate_exception_end(ctx, EXCP_RI);