diff --git a/qemu/aarch64.h b/qemu/aarch64.h
index faf713b0..54b121b0 100644
--- a/qemu/aarch64.h
+++ b/qemu/aarch64.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_aarch64
 #define tlb_add_large_page tlb_add_large_page_aarch64
 #define tlb_init tlb_init_aarch64
-#define tlb_fill tlb_fill_aarch64
 #define tlb_flush tlb_flush_aarch64
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64
 #define tlb_flush_entry tlb_flush_entry_aarch64
diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h
index ff0406ee..e43b140c 100644
--- a/qemu/aarch64eb.h
+++ b/qemu/aarch64eb.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_aarch64eb
 #define tlb_add_large_page tlb_add_large_page_aarch64eb
 #define tlb_init tlb_init_aarch64eb
-#define tlb_fill tlb_fill_aarch64eb
 #define tlb_flush tlb_flush_aarch64eb
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64eb
 #define tlb_flush_entry tlb_flush_entry_aarch64eb
diff --git a/qemu/accel/tcg/cputlb.c b/qemu/accel/tcg/cputlb.c
index c97df40c..7cb9a848 100644
--- a/qemu/accel/tcg/cputlb.c
+++ b/qemu/accel/tcg/cputlb.c
@@ -472,6 +472,25 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(struct uc_struct *uc, vo
     return ram_addr;
 }
 
+/*
+ * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
+ * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
+ * be discarded and looked up again (e.g. via tlb_entry()).
+ */
+static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
+                     MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
+{
+    CPUClass *cc = CPU_GET_CLASS(cpu->uc, cpu);
+    bool ok;
+
+    /*
+     * This is not a probe, so only valid return is success; failure
+     * should result in exception + longjmp to the cpu loop.
+     */
+    ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
+    assert(ok);
+}
+
 /* NOTE: this function can trigger an exception */
 /* NOTE2: the returned address is not exactly the physical address: it
  * is actually a ram_addr_t (in system mode; the user mode emulation
diff --git a/qemu/arm.h b/qemu/arm.h
index f2625bc2..6d073dfe 100644
--- a/qemu/arm.h
+++ b/qemu/arm.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_arm
 #define tlb_add_large_page tlb_add_large_page_arm
 #define tlb_init tlb_init_arm
-#define tlb_fill tlb_fill_arm
 #define tlb_flush tlb_flush_arm
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_arm
 #define tlb_flush_entry tlb_flush_entry_arm
diff --git a/qemu/armeb.h b/qemu/armeb.h
index 04c95ff9..b9afe067 100644
--- a/qemu/armeb.h
+++ b/qemu/armeb.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_armeb
 #define tlb_add_large_page tlb_add_large_page_armeb
 #define tlb_init tlb_init_armeb
-#define tlb_fill tlb_fill_armeb
 #define tlb_flush tlb_flush_armeb
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_armeb
 #define tlb_flush_entry tlb_flush_entry_armeb
diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 3bdd8474..d7e3dbaa 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -3239,7 +3239,6 @@ symbols = (
     'ti925t_initfn',
     'tlb_add_large_page',
     'tlb_init',
-    'tlb_fill',
     'tlb_flush',
     'tlb_flush_by_mmuidx',
     'tlb_flush_entry',
diff --git a/qemu/include/exec/exec-all.h b/qemu/include/exec/exec-all.h
index ab58740c..d94b3675 100644
--- a/qemu/include/exec/exec-all.h
+++ b/qemu/include/exec/exec-all.h
@@ -353,14 +353,6 @@ void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align));
  */
 struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
                                              hwaddr index, MemTxAttrs attrs);
-
-/*
- * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
- * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
- * be discarded and looked up again (e.g. via tlb_entry()).
- */
-void tlb_fill(CPUState *cpu, target_ulong addr, int size,
-              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
 #endif
 
 #if defined(CONFIG_USER_ONLY)
diff --git a/qemu/m68k.h b/qemu/m68k.h
index 080e9f2c..6be854e8 100644
--- a/qemu/m68k.h
+++ b/qemu/m68k.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_m68k
 #define tlb_add_large_page tlb_add_large_page_m68k
 #define tlb_init tlb_init_m68k
-#define tlb_fill tlb_fill_m68k
 #define tlb_flush tlb_flush_m68k
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_m68k
 #define tlb_flush_entry tlb_flush_entry_m68k
diff --git a/qemu/mips.h b/qemu/mips.h
index da0de825..4e99a5c9 100644
--- a/qemu/mips.h
+++ b/qemu/mips.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_mips
 #define tlb_add_large_page tlb_add_large_page_mips
 #define tlb_init tlb_init_mips
-#define tlb_fill tlb_fill_mips
 #define tlb_flush tlb_flush_mips
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips
 #define tlb_flush_entry tlb_flush_entry_mips
diff --git a/qemu/mips64.h b/qemu/mips64.h
index b17b7267..3542fc91 100644
--- a/qemu/mips64.h
+++ b/qemu/mips64.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_mips64
 #define tlb_add_large_page tlb_add_large_page_mips64
 #define tlb_init tlb_init_mips64
-#define tlb_fill tlb_fill_mips64
 #define tlb_flush tlb_flush_mips64
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64
 #define tlb_flush_entry tlb_flush_entry_mips64
diff --git a/qemu/mips64el.h b/qemu/mips64el.h
index 0a9583fa..a55fc352 100644
--- a/qemu/mips64el.h
+++ b/qemu/mips64el.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_mips64el
 #define tlb_add_large_page tlb_add_large_page_mips64el
 #define tlb_init tlb_init_mips64el
-#define tlb_fill tlb_fill_mips64el
 #define tlb_flush tlb_flush_mips64el
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64el
 #define tlb_flush_entry tlb_flush_entry_mips64el
diff --git a/qemu/mipsel.h b/qemu/mipsel.h
index 7c184995..33268177 100644
--- a/qemu/mipsel.h
+++ b/qemu/mipsel.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_mipsel
 #define tlb_add_large_page tlb_add_large_page_mipsel
 #define tlb_init tlb_init_mipsel
-#define tlb_fill tlb_fill_mipsel
 #define tlb_flush tlb_flush_mipsel
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mipsel
 #define tlb_flush_entry tlb_flush_entry_mipsel
diff --git a/qemu/powerpc.h b/qemu/powerpc.h
index 645afa23..f17b4c8e 100644
--- a/qemu/powerpc.h
+++ b/qemu/powerpc.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_powerpc
 #define tlb_add_large_page tlb_add_large_page_powerpc
 #define tlb_init tlb_init_powerpc
-#define tlb_fill tlb_fill_powerpc
 #define tlb_flush tlb_flush_powerpc
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_powerpc
 #define tlb_flush_entry tlb_flush_entry_powerpc
diff --git a/qemu/riscv32.h b/qemu/riscv32.h
index 993149b0..e654d126 100644
--- a/qemu/riscv32.h
+++ b/qemu/riscv32.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_riscv32
 #define tlb_add_large_page tlb_add_large_page_riscv32
 #define tlb_init tlb_init_riscv32
-#define tlb_fill tlb_fill_riscv32
 #define tlb_flush tlb_flush_riscv32
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_riscv32
 #define tlb_flush_entry tlb_flush_entry_riscv32
diff --git a/qemu/riscv64.h b/qemu/riscv64.h
index 98fc1eeb..40843c62 100644
--- a/qemu/riscv64.h
+++ b/qemu/riscv64.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_riscv64
 #define tlb_add_large_page tlb_add_large_page_riscv64
 #define tlb_init tlb_init_riscv64
-#define tlb_fill tlb_fill_riscv64
 #define tlb_flush tlb_flush_riscv64
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_riscv64
 #define tlb_flush_entry tlb_flush_entry_riscv64
diff --git a/qemu/sparc.h b/qemu/sparc.h
index 67adbba8..87281f64 100644
--- a/qemu/sparc.h
+++ b/qemu/sparc.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_sparc
 #define tlb_add_large_page tlb_add_large_page_sparc
 #define tlb_init tlb_init_sparc
-#define tlb_fill tlb_fill_sparc
 #define tlb_flush tlb_flush_sparc
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc
 #define tlb_flush_entry tlb_flush_entry_sparc
diff --git a/qemu/sparc64.h b/qemu/sparc64.h
index 66b9f94f..bc6120cc 100644
--- a/qemu/sparc64.h
+++ b/qemu/sparc64.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_sparc64
 #define tlb_add_large_page tlb_add_large_page_sparc64
 #define tlb_init tlb_init_sparc64
-#define tlb_fill tlb_fill_sparc64
 #define tlb_flush tlb_flush_sparc64
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc64
 #define tlb_flush_entry tlb_flush_entry_sparc64
diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c
index 37ed6027..20c75008 100644
--- a/qemu/target/arm/helper.c
+++ b/qemu/target/arm/helper.c
@@ -12891,14 +12891,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 #endif
 }
 
-#ifndef CONFIG_USER_ONLY
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
-              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
-    arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
-}
-#endif
-
 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
 {
     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
diff --git a/qemu/target/i386/excp_helper.c b/qemu/target/i386/excp_helper.c
index 7c8953eb..649491bb 100644
--- a/qemu/target/i386/excp_helper.c
+++ b/qemu/target/i386/excp_helper.c
@@ -702,11 +702,3 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
     return true;
 #endif
 }
-
-#if !defined(CONFIG_USER_ONLY)
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
-              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
-    x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
-}
-#endif
diff --git a/qemu/target/m68k/helper.c b/qemu/target/m68k/helper.c
index d2e34503..88587159 100644
--- a/qemu/target/m68k/helper.c
+++ b/qemu/target/m68k/helper.c
@@ -530,14 +530,6 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     cpu_loop_exit_restore(cs, retaddr);
 }
 
-#ifndef CONFIG_USER_ONLY
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
-              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
-    m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
-}
-#endif
-
 uint32_t HELPER(bitrev)(uint32_t x)
 {
     x = ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau);
diff --git a/qemu/target/mips/helper.c b/qemu/target/mips/helper.c
index 20787f69..187d4914 100644
--- a/qemu/target/mips/helper.c
+++ b/qemu/target/mips/helper.c
@@ -931,12 +931,6 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 }
 
 #ifndef CONFIG_USER_ONLY
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
-              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
-    mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
-}
-
 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 {
     hwaddr physical;
diff --git a/qemu/target/riscv/cpu_helper.c b/qemu/target/riscv/cpu_helper.c
index 7d1bb1ce..c4dc6df6 100644
--- a/qemu/target/riscv/cpu_helper.c
+++ b/qemu/target/riscv/cpu_helper.c
@@ -379,12 +379,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
     env->badaddr = addr;
     riscv_raise_exception(env, cs->exception_index, retaddr);
 }
-
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
-        MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
-    riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
-}
 #endif
 
 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
diff --git a/qemu/target/sparc/ldst_helper.c b/qemu/target/sparc/ldst_helper.c
index 70cabc26..0a32553a 100644
--- a/qemu/target/sparc/ldst_helper.c
+++ b/qemu/target/sparc/ldst_helper.c
@@ -1929,10 +1929,4 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 #endif
     cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
 }
-
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
-              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
-    sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
-}
 #endif
diff --git a/qemu/x86_64.h b/qemu/x86_64.h
index 6e002b64..58378ce6 100644
--- a/qemu/x86_64.h
+++ b/qemu/x86_64.h
@@ -3233,7 +3233,6 @@
 #define ti925t_initfn ti925t_initfn_x86_64
 #define tlb_add_large_page tlb_add_large_page_x86_64
 #define tlb_init tlb_init_x86_64
-#define tlb_fill tlb_fill_x86_64
 #define tlb_flush tlb_flush_x86_64
 #define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_x86_64
 #define tlb_flush_entry tlb_flush_entry_x86_64