diff --git a/qemu/aarch64.h b/qemu/aarch64.h
index 0f5b6795..4d4836a4 100644
--- a/qemu/aarch64.h
+++ b/qemu/aarch64.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_aarch64
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_aarch64
 #define deregister_tm_clones deregister_tm_clones_aarch64
+#define devend_memop devend_memop_aarch64
 #define device_class_base_init device_class_base_init_aarch64
 #define device_class_init device_class_init_aarch64
 #define device_finalize device_finalize_aarch64
diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h
index 0b34b503..eb5bdce7 100644
--- a/qemu/aarch64eb.h
+++ b/qemu/aarch64eb.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_aarch64eb
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_aarch64eb
 #define deregister_tm_clones deregister_tm_clones_aarch64eb
+#define devend_memop devend_memop_aarch64eb
 #define device_class_base_init device_class_base_init_aarch64eb
 #define device_class_init device_class_init_aarch64eb
 #define device_finalize device_finalize_aarch64eb
diff --git a/qemu/accel/tcg/cputlb.c b/qemu/accel/tcg/cputlb.c
index fa578962..6adf9621 100644
--- a/qemu/accel/tcg/cputlb.c
+++ b/qemu/accel/tcg/cputlb.c
@@ -605,7 +605,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
     cpu->mem_io_vaddr = addr;
     cpu->mem_io_access_type = access_type;
 
-    r = memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size),
+    r = memory_region_dispatch_read(mr, mr_offset, &val,
+                                    size_memop(size) | MO_TE,
                                     iotlbentry->attrs);
     if (r != MEMTX_OK) {
         hwaddr physaddr = mr_offset +
@@ -636,7 +637,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
     }
     cpu->mem_io_vaddr = addr;
     cpu->mem_io_pc = retaddr;
-    r = memory_region_dispatch_write(mr, mr_offset, val, size_memop(size),
+    r = memory_region_dispatch_write(mr, mr_offset, val,
+                                     size_memop(size) | MO_TE,
                                      iotlbentry->attrs);
     if (r != MEMTX_OK) {
         hwaddr physaddr = mr_offset +
@@ -1045,6 +1047,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
             }
         }
 
+        /* TODO: Merge bswap into io_readx -> memory_region_dispatch_read.  */
         res = io_readx(env, &env->iotlb[mmu_idx][index], mmu_idx, addr,
                        retaddr, access_type, size);
         return handle_bswap(res, size, big_endian);
@@ -1367,6 +1370,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
             }
         }
 
+        /* TODO: Merge bswap into io_writex -> memory_region_dispatch_write.  */
         io_writex(env, &env->iotlb[mmu_idx][index], mmu_idx,
                   handle_bswap(val, size, big_endian),
                   addr, retaddr, size);
diff --git a/qemu/arm.h b/qemu/arm.h
index fb9a50ac..4b884029 100644
--- a/qemu/arm.h
+++ b/qemu/arm.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_arm
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_arm
 #define deregister_tm_clones deregister_tm_clones_arm
+#define devend_memop devend_memop_arm
 #define device_class_base_init device_class_base_init_arm
 #define device_class_init device_class_init_arm
 #define device_finalize device_finalize_arm
diff --git a/qemu/armeb.h b/qemu/armeb.h
index 8be86e83..e0a2da5b 100644
--- a/qemu/armeb.h
+++ b/qemu/armeb.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_armeb
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_armeb
 #define deregister_tm_clones deregister_tm_clones_armeb
+#define devend_memop devend_memop_armeb
 #define device_class_base_init device_class_base_init_armeb
 #define device_class_init device_class_init_armeb
 #define device_finalize device_finalize_armeb
diff --git a/qemu/exec.c b/qemu/exec.c
index b64992cd..17b566c2 100644
--- a/qemu/exec.c
+++ b/qemu/exec.c
@@ -1960,8 +1960,13 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
             /* XXX: could force current_cpu to NULL to avoid
                potential bugs */
             val = ldn_p(buf, l);
+            /*
+             * TODO: Merge bswap from ldn_p into memory_region_dispatch_write
+             * by using ldn_he_p and dropping MO_TE to get a host-endian value.
+             */
             result |= memory_region_dispatch_write(mr, addr1, val,
-                                                   size_memop(l), attrs);
+                                                   size_memop(l) | MO_TE,
+                                                   attrs);
         } else {
             /* RAM case */
             ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
@@ -2037,8 +2042,12 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
             // Unicorn: commented out
             //release_lock |= prepare_mmio_access(mr);
             l = memory_access_size(mr, l, addr1);
+            /*
+             * TODO: Merge bswap from stn_p into memory_region_dispatch_read
+             * by using stn_he_p and dropping MO_TE to get a host-endian value.
+             */
             result |= memory_region_dispatch_read(mr, addr1, &val,
-                                                  size_memop(l), attrs);
+                                                  size_memop(l) | MO_TE, attrs);
             stn_p(buf, l, val);
         } else {
             /* RAM case */
diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 44dd88a4..d22e875a 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -361,6 +361,7 @@ symbols = (
     'define_one_arm_cp_reg',
     'define_one_arm_cp_reg_with_opaque',
     'deregister_tm_clones',
+    'devend_memop',
     'device_class_base_init',
     'device_class_init',
     'device_finalize',
diff --git a/qemu/include/exec/memory.h b/qemu/include/exec/memory.h
index 7fc90583..0e99eddf 100644
--- a/qemu/include/exec/memory.h
+++ b/qemu/include/exec/memory.h
@@ -1434,6 +1434,9 @@ address_space_write_cached(MemoryRegionCache *cache, hwaddr addr,
 
 void unicorn_free_empty_flat_view(struct uc_struct *uc);
 
+/* enum device_endian to MemOp.  */
+MemOp devend_memop(enum device_endian end);
+
 #endif
 
 #endif
diff --git a/qemu/m68k.h b/qemu/m68k.h
index 54be6c1c..a0ea088d 100644
--- a/qemu/m68k.h
+++ b/qemu/m68k.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_m68k
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_m68k
 #define deregister_tm_clones deregister_tm_clones_m68k
+#define devend_memop devend_memop_m68k
 #define device_class_base_init device_class_base_init_m68k
 #define device_class_init device_class_init_m68k
 #define device_finalize device_finalize_m68k
diff --git a/qemu/memory.c b/qemu/memory.c
index ccf04d38..ffd8e551 100644
--- a/qemu/memory.c
+++ b/qemu/memory.c
@@ -2044,3 +2044,20 @@ void memory_register_types(struct uc_struct *uc)
     type_register_static(uc, &memory_region_info);
 }
 
+MemOp devend_memop(enum device_endian end)
+{
+    static MemOp conv[] = {
+        [DEVICE_LITTLE_ENDIAN] = MO_LE,
+        [DEVICE_BIG_ENDIAN] = MO_BE,
+        [DEVICE_NATIVE_ENDIAN] = MO_TE,
+        [DEVICE_HOST_ENDIAN] = 0,
+    };
+    switch (end) {
+    case DEVICE_LITTLE_ENDIAN:
+    case DEVICE_BIG_ENDIAN:
+    case DEVICE_NATIVE_ENDIAN:
+        return conv[end];
+    default:
+        g_assert_not_reached();
+    }
+}
diff --git a/qemu/memory_ldst.inc.c b/qemu/memory_ldst.inc.c
index e7169ad5..8388f8fa 100644
--- a/qemu/memory_ldst.inc.c
+++ b/qemu/memory_ldst.inc.c
@@ -42,7 +42,9 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
         //release_lock |= prepare_mmio_access(mr);
 
         /* I/O case */
-        r = memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs);
+        /* TODO: Merge bswap32 into memory_region_dispatch_read.  */
+        r = memory_region_dispatch_read(mr, addr1, &val,
+                                        MO_32 | devend_memop(endian), attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian == DEVICE_LITTLE_ENDIAN) {
             val = bswap32(val);
@@ -142,7 +144,9 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
         //release_lock |= prepare_mmio_access(mr);
 
         /* I/O case */
-        r = memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs);
+        /* TODO: Merge bswap64 into memory_region_dispatch_read.  */
+        r = memory_region_dispatch_read(mr, addr1, &val,
+                                        MO_64 | devend_memop(endian), attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian == DEVICE_LITTLE_ENDIAN) {
             val = bswap64(val);
@@ -288,7 +292,9 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
         //release_lock |= prepare_mmio_access(mr);
 
         /* I/O case */
-        r = memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs);
+        /* TODO: Merge bswap16 into memory_region_dispatch_read.  */
+        r = memory_region_dispatch_read(mr, addr1, &val,
+                                        MO_16 | devend_memop(endian), attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian == DEVICE_LITTLE_ENDIAN) {
             val = bswap16(val);
@@ -440,7 +446,9 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
             val = bswap32(val);
         }
 #endif
-        r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs);
+        /* TODO: Merge bswap32 into memory_region_dispatch_write.  */
+        r = memory_region_dispatch_write(mr, addr1, val,
+                                         MO_32 | devend_memop(endian), attrs);
     } else {
         /* RAM case */
         ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
@@ -581,7 +589,9 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
             val = bswap16(val);
         }
 #endif
-        r = memory_region_dispatch_write(mr, addr1, val, MO_16, attrs);
+        /* TODO: Merge bswap16 into memory_region_dispatch_write.  */
+        r = memory_region_dispatch_write(mr, addr1, val,
+                                         MO_16 | devend_memop(endian), attrs);
     } else {
         /* RAM case */
         ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
@@ -678,7 +688,9 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
             val = bswap64(val);
         }
 #endif
-        r = memory_region_dispatch_write(mr, addr1, val, MO_64, attrs);
+        /* TODO: Merge bswap64 into memory_region_dispatch_write.  */
+        r = memory_region_dispatch_write(mr, addr1, val,
+                                         MO_64 | devend_memop(endian), attrs);
     } else {
         /* RAM case */
         ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
diff --git a/qemu/mips.h b/qemu/mips.h
index eff998fd..c03662c5 100644
--- a/qemu/mips.h
+++ b/qemu/mips.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_mips
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_mips
 #define deregister_tm_clones deregister_tm_clones_mips
+#define devend_memop devend_memop_mips
 #define device_class_base_init device_class_base_init_mips
 #define device_class_init device_class_init_mips
 #define device_finalize device_finalize_mips
diff --git a/qemu/mips64.h b/qemu/mips64.h
index 4cf01564..db1ea742 100644
--- a/qemu/mips64.h
+++ b/qemu/mips64.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_mips64
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_mips64
 #define deregister_tm_clones deregister_tm_clones_mips64
+#define devend_memop devend_memop_mips64
 #define device_class_base_init device_class_base_init_mips64
 #define device_class_init device_class_init_mips64
 #define device_finalize device_finalize_mips64
diff --git a/qemu/mips64el.h b/qemu/mips64el.h
index 9e146b9e..9b6d2068 100644
--- a/qemu/mips64el.h
+++ b/qemu/mips64el.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_mips64el
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_mips64el
 #define deregister_tm_clones deregister_tm_clones_mips64el
+#define devend_memop devend_memop_mips64el
 #define device_class_base_init device_class_base_init_mips64el
 #define device_class_init device_class_init_mips64el
 #define device_finalize device_finalize_mips64el
diff --git a/qemu/mipsel.h b/qemu/mipsel.h
index d927507d..76019041 100644
--- a/qemu/mipsel.h
+++ b/qemu/mipsel.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_mipsel
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_mipsel
 #define deregister_tm_clones deregister_tm_clones_mipsel
+#define devend_memop devend_memop_mipsel
 #define device_class_base_init device_class_base_init_mipsel
 #define device_class_init device_class_init_mipsel
 #define device_finalize device_finalize_mipsel
diff --git a/qemu/powerpc.h b/qemu/powerpc.h
index fde3cd02..bd89cef3 100644
--- a/qemu/powerpc.h
+++ b/qemu/powerpc.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_powerpc
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_powerpc
 #define deregister_tm_clones deregister_tm_clones_powerpc
+#define devend_memop devend_memop_powerpc
 #define device_class_base_init device_class_base_init_powerpc
 #define device_class_init device_class_init_powerpc
 #define device_finalize device_finalize_powerpc
diff --git a/qemu/riscv32.h b/qemu/riscv32.h
index 63eb681d..fbc3cd0d 100644
--- a/qemu/riscv32.h
+++ b/qemu/riscv32.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_riscv32
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_riscv32
 #define deregister_tm_clones deregister_tm_clones_riscv32
+#define devend_memop devend_memop_riscv32
 #define device_class_base_init device_class_base_init_riscv32
 #define device_class_init device_class_init_riscv32
 #define device_finalize device_finalize_riscv32
diff --git a/qemu/riscv64.h b/qemu/riscv64.h
index 8b805c8a..e0343c33 100644
--- a/qemu/riscv64.h
+++ b/qemu/riscv64.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_riscv64
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_riscv64
 #define deregister_tm_clones deregister_tm_clones_riscv64
+#define devend_memop devend_memop_riscv64
 #define device_class_base_init device_class_base_init_riscv64
 #define device_class_init device_class_init_riscv64
 #define device_finalize device_finalize_riscv64
diff --git a/qemu/sparc.h b/qemu/sparc.h
index a102528d..2f02c535 100644
--- a/qemu/sparc.h
+++ b/qemu/sparc.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_sparc
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_sparc
 #define deregister_tm_clones deregister_tm_clones_sparc
+#define devend_memop devend_memop_sparc
 #define device_class_base_init device_class_base_init_sparc
 #define device_class_init device_class_init_sparc
 #define device_finalize device_finalize_sparc
diff --git a/qemu/sparc64.h b/qemu/sparc64.h
index cdf342a6..3b45bcc2 100644
--- a/qemu/sparc64.h
+++ b/qemu/sparc64.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_sparc64
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_sparc64
 #define deregister_tm_clones deregister_tm_clones_sparc64
+#define devend_memop devend_memop_sparc64
 #define device_class_base_init device_class_base_init_sparc64
 #define device_class_init device_class_init_sparc64
 #define device_finalize device_finalize_sparc64
diff --git a/qemu/x86_64.h b/qemu/x86_64.h
index 11d19726..0ec999bd 100644
--- a/qemu/x86_64.h
+++ b/qemu/x86_64.h
@@ -355,6 +355,7 @@
 #define define_one_arm_cp_reg define_one_arm_cp_reg_x86_64
 #define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_x86_64
 #define deregister_tm_clones deregister_tm_clones_x86_64
+#define devend_memop devend_memop_x86_64
 #define device_class_base_init device_class_base_init_x86_64
 #define device_class_init device_class_init_x86_64
 #define device_finalize device_finalize_x86_64