From da652cb603a80a2958c4a4a6cfb887652f738529 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Tue, 30 Mar 2021 14:59:30 -0400 Subject: [PATCH] target/riscv: fix vs() to return proper error code vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature is not enabled. If -1 is returned, exception will be raised and cs->exception_index will be set to the negative return value. The exception will then be treated as an instruction access fault instead of illegal instruction fault. Backports 5e437d3ccdccfd85f6e69ca60f921be2dab62c3c --- qemu/target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target/riscv/csr.c b/qemu/target/riscv/csr.c index ef5e1cf1..aa2f027e 100644 --- a/qemu/target/riscv/csr.c +++ b/qemu/target/riscv/csr.c @@ -61,7 +61,7 @@ static int vs(CPURISCVState *env, int csrno) if (env->misa & RVV) { return 0; } - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } static int ctr(CPURISCVState *env, int csrno)