diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h
index b89d9290..bc67b95e 100644
--- a/qemu/target/arm/cpu.h
+++ b/qemu/target/arm/cpu.h
@@ -371,8 +371,8 @@ typedef struct CPUARMState {
         uint32_t c9_data;
         uint64_t c9_pmcr; /* performance monitor control register */
         uint64_t c9_pmcnten; /* perf monitor counter enables */
-        uint32_t c9_pmovsr; /* perf monitor overflow status */
-        uint32_t c9_pmuserenr; /* perf monitor user enable */
+        uint64_t c9_pmovsr; /* perf monitor overflow status */
+        uint64_t c9_pmuserenr; /* perf monitor user enable */
         uint64_t c9_pmselr; /* perf monitor counter selection register */
         uint64_t c9_pminten; /* perf monitor interrupt enables */
         union { /* Memory attribute redirection */
diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c
index 48b7e517..6b0536e2 100644
--- a/qemu/target/arm/helper.c
+++ b/qemu/target/arm/helper.c
@@ -1189,7 +1189,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       ARM_CP_ALIAS, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmcnten), {0, 0},
       pmreg_access, NULL, pmcntenclr_write },
     { "PMOVSR", 15,9,12, 0,0,3, 0,
-      0, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmovsr), {0, 0},
+      0, PL0_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pmovsr), {0, 0},
       pmreg_access, NULL, pmovsr_write, NULL, raw_write },
     { "PMOVSCLR_EL0", 0,9,12, 3,3,3, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
       PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmovsr), {0, 0},
@@ -1226,7 +1226,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       ARM_CP_CONST, PL0_RW, 0, NULL, 0, 0, {0, 0},
       pmreg_access_xevcntr },
     { "PMUSERENR", 15,9,14, 0,0,0, 0,
-      0, PL0_R | PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmuserenr), {0, 0},
+      0, PL0_R | PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pmuserenr), {0, 0},
       access_tpm, NULL, pmuserenr_write, NULL, raw_write },
     { "PMUSERENR_EL0", 0,9,14,3,3,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
       PL0_R | PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmuserenr), {0, 0},