From d2cea344f0683cbdcf7e9505b6253ae3ad0c3e4c Mon Sep 17 00:00:00 2001 From: Georg Kotheimer Date: Mon, 8 Mar 2021 14:40:27 -0500 Subject: [PATCH] target/riscv: Fix implementation of HLVX.WU instruction The HLVX.WU instruction is supposed to read a machine word, but prior to this change it read a byte instead. Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv instructions") Backports 1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa --- qemu/target/riscv/op_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qemu/target/riscv/op_helper.c b/qemu/target/riscv/op_helper.c index 64918d4a..87239a0b 100644 --- a/qemu/target/riscv/op_helper.c +++ b/qemu/target/riscv/op_helper.c @@ -335,12 +335,12 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, riscv_cpu_set_two_stage_lookup(env, true); switch (memop) { - case MO_TEUL: - pte = cpu_ldl_mmuidx_ra(env, address, cpu_mmu_index(env, true), GETPC()); - break; case MO_TEUW: pte = cpu_lduw_mmuidx_ra(env, address, cpu_mmu_index(env, true), GETPC()); break; + case MO_TEUL: + pte = cpu_ldl_mmuidx_ra(env, address, cpu_mmu_index(env, true), GETPC()); + break; default: g_assert_not_reached(); }