From cfefada2968f2ee9a7f77b47b99c7e4c84a7a316 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 3 Mar 2021 17:50:24 -0500 Subject: [PATCH] target/arm: Implement v8.1M PXN extension In v8.1M the PXN architecture extension adds a new PXN bit to the MPU_RLAR registers, which forbids execution of code in the region from a privileged mode. This is another feature which is just in the generic "in v8.1M" set and has no ID register field indicating its presence. Backports cad8e2e3160dd10371552fce6cd8c6e171503e13 --- qemu/target/arm/helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 8e102db2..2829489d 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -11478,6 +11478,11 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, } else { uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); + bool pxn = false; + + if (arm_feature(env, ARM_FEATURE_V8_1M)) { + pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); + } if (m_is_system_region(env, address)) { /* System space is always execute never */ @@ -11485,7 +11490,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, } *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); - if (*prot && !xn) { + if (*prot && !xn && !(pxn && !is_user)) { *prot |= PAGE_EXEC; } /*