From ce25609ed37ae975416d1602aa8317ce54c28644 Mon Sep 17 00:00:00 2001
From: Laurent Vivier <laurent@vivier.eu>
Date: Sat, 3 Mar 2018 14:26:29 -0500
Subject: [PATCH] target/m68k: implement rtd

Add "Return and Deallocate" (rtd) instruction.

RTD #d

(SP) -> PC
SP + 4 + d -> SP

Backports commit 18059c9e1648bf4fc5c7c1bae6f54690742b05ba from qemu
---
 qemu/target/m68k/cpu.c       |  2 ++
 qemu/target/m68k/cpu.h       |  1 +
 qemu/target/m68k/translate.c | 12 ++++++++++++
 3 files changed, 15 insertions(+)

diff --git a/qemu/target/m68k/cpu.c b/qemu/target/m68k/cpu.c
index 86a84a5f..b8b5e085 100644
--- a/qemu/target/m68k/cpu.c
+++ b/qemu/target/m68k/cpu.c
@@ -120,6 +120,7 @@ static void m68020_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     m68k_set_feature(env, M68K_FEATURE_FPU);
     m68k_set_feature(env, M68K_FEATURE_CAS);
     m68k_set_feature(env, M68K_FEATURE_BKPT);
+    m68k_set_feature(env, M68K_FEATURE_RTD);
 }
 #define m68030_cpu_initfn m68020_cpu_initfn
 #define m68040_cpu_initfn m68020_cpu_initfn
@@ -141,6 +142,7 @@ static void m68060_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     m68k_set_feature(env, M68K_FEATURE_FPU);
     m68k_set_feature(env, M68K_FEATURE_CAS);
     m68k_set_feature(env, M68K_FEATURE_BKPT);
+    m68k_set_feature(env, M68K_FEATURE_RTD);
 }
 
 static void m5208_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
diff --git a/qemu/target/m68k/cpu.h b/qemu/target/m68k/cpu.h
index bbe2e33c..e80e5a59 100644
--- a/qemu/target/m68k/cpu.h
+++ b/qemu/target/m68k/cpu.h
@@ -248,6 +248,7 @@ enum m68k_features {
     M68K_FEATURE_FPU,
     M68K_FEATURE_CAS,
     M68K_FEATURE_BKPT,
+    M68K_FEATURE_RTD,
 };
 
 static inline int m68k_feature(CPUM68KState *env, int feature)
diff --git a/qemu/target/m68k/translate.c b/qemu/target/m68k/translate.c
index d225f07b..ee10a38f 100644
--- a/qemu/target/m68k/translate.c
+++ b/qemu/target/m68k/translate.c
@@ -2550,6 +2550,17 @@ DISAS_INSN(nop)
 {
 }
 
+DISAS_INSN(rtd)
+{
+    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    TCGv tmp;
+    int16_t offset = read_im16(env, s);
+
+    tmp = gen_load(s, OS_LONG, QREG_SP, 0);
+    tcg_gen_addi_i32(tcg_ctx,QREG_SP, QREG_SP, offset + 4);
+    gen_jmp(s, tmp);
+}
+
 DISAS_INSN(rts)
 {
     TCGContext *tcg_ctx = s->uc->tcg_ctx;
@@ -5076,6 +5087,7 @@ void register_m68k_insns (CPUM68KState *env)
     BASE(nop,       4e71, ffff);
     BASE(stop,      4e72, ffff);
     BASE(rte,       4e73, ffff);
+    INSN(rtd,       4e74, ffff, RTD);
     BASE(rts,       4e75, ffff);
     INSN(movec,     4e7b, ffff, CF_ISA_A);
     BASE(jump,      4e80, ffc0);