From cde007ccb6538a26fac8565b9ad65745d8d78cb9 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Mon, 8 Mar 2021 12:41:17 -0500 Subject: [PATCH] target/riscv: check before allocating TCG temps Backports ec80f8745931f0c8f8f2251e16bcc69170cf6f27 --- qemu/target/riscv/insn_trans/trans_rvd.inc.c | 8 ++++---- qemu/target/riscv/insn_trans/trans_rvf.inc.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/qemu/target/riscv/insn_trans/trans_rvd.inc.c b/qemu/target/riscv/insn_trans/trans_rvd.inc.c index c66c5399..168aef9d 100644 --- a/qemu/target/riscv/insn_trans/trans_rvd.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvd.inc.c @@ -22,10 +22,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) { TCGContext *tcg_ctx = ctx->uc->tcg_ctx; - TCGv t0 = tcg_temp_new(tcg_ctx); - gen_get_gpr(ctx, t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + TCGv t0 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, t0, a->rs1); tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm); tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rd], t0, ctx->mem_idx, MO_TEQ); @@ -39,10 +39,10 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) { TCGContext *tcg_ctx = ctx->uc->tcg_ctx; - TCGv t0 = tcg_temp_new(tcg_ctx); - gen_get_gpr(ctx, t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + TCGv t0 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, t0, a->rs1); tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm); tcg_gen_qemu_st_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rs2], t0, ctx->mem_idx, MO_TEQ); diff --git a/qemu/target/riscv/insn_trans/trans_rvf.inc.c b/qemu/target/riscv/insn_trans/trans_rvf.inc.c index 83d5ce90..cf4e3ec6 100644 --- a/qemu/target/riscv/insn_trans/trans_rvf.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvf.inc.c @@ -26,10 +26,10 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGContext *tcg_ctx = ctx->uc->tcg_ctx; - TCGv t0 = tcg_temp_new(tcg_ctx); - gen_get_gpr(ctx, t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv t0 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, t0, a->rs1); tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm); tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rd], t0, ctx->mem_idx, MO_TEUL); @@ -43,11 +43,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); TCGv t0 = tcg_temp_new(tcg_ctx); gen_get_gpr(ctx, t0, a->rs1); - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm); tcg_gen_qemu_st_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rs2], t0, ctx->mem_idx, MO_TEUL);