From cb324fd0397cfd4946308f1fd3e115911879be1f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 8 May 2018 08:25:24 -0400 Subject: [PATCH] target/arm: Tidy conditions in handle_vec_simd_shri The (size > 3 && !is_q) condition is identical to the preceeding test of bit 3 in immh; eliminate it. For the benefit of Coverity, assert that size is within the bounds we expect. Fixes: Coverity CID1385846 Fixes: Coverity CID1385849 Fixes: Coverity CID1385852 Fixes: Coverity CID1385857 Backports commit 8dae46970532afcf93470b00e83ca9921980efc3 from qemu --- qemu/target/arm/translate-a64.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index e7bc82cb..b9b5c744 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -9151,10 +9151,7 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, return; } - if (size > 3 && !is_q) { - unallocated_encoding(s); - return; - } + tcg_debug_assert(size <= 3); if (!fp_access_check(s)) { return;