From cb11b3a6bd23f546e39283a4d41c0b6ac01b7528 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Aug 2018 13:57:49 -0400 Subject: [PATCH] target/arm: Add sve-max-vq cpu property to -cpu max This allows the default (and maximum) vector length to be set from the command-line. Which is extraordinarily helpful in debugging problems depending on vector length without having to bake knowledge of PR_SET_SVE_VL into every guest binary. Backports relevant parts of commit adf92eab90e3f5f34c285da6d14d48952b7a8e72 from qemu --- qemu/target/arm/cpu.c | 6 +++--- qemu/target/arm/cpu.h | 3 +++ qemu/target/arm/cpu64.c | 2 ++ 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index 8c2b93a2..101220b9 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -160,9 +160,9 @@ static void arm_cpu_reset(CPUState *s) env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cptr_el[3] |= CPTR_EZ; /* with maximum vector length */ - env->vfp.zcr_el[1] = ARM_MAX_VQ - 1; - env->vfp.zcr_el[2] = ARM_MAX_VQ - 1; - env->vfp.zcr_el[3] = ARM_MAX_VQ - 1; + env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; + env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; + env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index bbbac208..bcaf999f 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -827,6 +827,9 @@ typedef struct ARMCPU { QLIST_HEAD(, ARMELChangeHook) el_change_hooks; int32_t node_id; /* NUMA node this CPU belongs to */ + + /* Used to set the maximum vector length the cpu will support. */ + uint32_t sve_max_vq; } ARMCPU; static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/qemu/target/arm/cpu64.c b/qemu/target/arm/cpu64.c index 9d8a3c74..6595ffdb 100644 --- a/qemu/target/arm/cpu64.c +++ b/qemu/target/arm/cpu64.c @@ -225,6 +225,8 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque) */ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ + + cpu->sve_max_vq = ARM_MAX_VQ; } typedef struct ARMCPUInfo {