From c50f8c9d931cd4ad5f7fddc1925540ab4195e381 Mon Sep 17 00:00:00 2001 From: Yifei Jiang Date: Mon, 8 Mar 2021 15:15:59 -0500 Subject: [PATCH] target/riscv: Fix the bug of HLVX/HLV/HSV We found that the hypervisor virtual-machine load and store instructions, included HLVX/HLV/HSV, couldn't access guest userspace memory. In the riscv-privileged spec, HLVX/HLV/HSV is defined as follow: "As usual when V=1, two-stage address translation is applied, and the HS-level sstatus.SUM is ignored." But get_physical_address() doesn't ignore sstatus.SUM, when HLVX/HLV/HSV accesses guest userspace memory. So this patch fixes it. Backports c63ca4ff7f81116c26984973052991ff0bd7caec --- qemu/target/riscv/cpu_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qemu/target/riscv/cpu_helper.c b/qemu/target/riscv/cpu_helper.c index 4a63457d..2fcd2156 100644 --- a/qemu/target/riscv/cpu_helper.c +++ b/qemu/target/riscv/cpu_helper.c @@ -361,7 +361,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, vm = get_field(env->hgatp, HGATP_MODE); widened = 2; } - sum = get_field(env->mstatus, MSTATUS_SUM); + /* status.SUM will be ignored if execute on background */ + sum = get_field(env->mstatus, MSTATUS_SUM) || use_background; switch (vm) { case VM_1_10_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;