diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c
index 2fd2349c..b889a91c 100644
--- a/qemu/target-arm/helper.c
+++ b/qemu/target-arm/helper.c
@@ -2062,7 +2062,23 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
     REGINFO_SENTINEL
 };
 
-static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
+static const ARMCPRegInfo el3_cp_reginfo[] = {
+    { "SCR_EL3", 0,1,1, 3,6,0, ARM_CP_STATE_AA64,0,
+      PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.scr_el3), {0, 0},
+      NULL, NULL, scr_write },
+    { "SCR", 15,1,1, 0,0,0, 0,ARM_CP_NO_MIGRATE,
+      PL3_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0},
+      NULL, NULL, scr_write, NULL, NULL, arm_cp_reset_ignore },
+    { "SDER32_EL3", 0,1,1, 3,6,1, ARM_CP_STATE_AA64,0,
+      PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sder) },
+    { "SDER", 15,1,1, 0,0,1, 0,0,
+      PL3_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.sder) },
+      /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
+    { "NSACR", 15,1,1, 0,0,2, 0,0,
+      PL3_W | PL1_R, 0, NULL, 0, offsetof(CPUARMState, cp15.nsacr) },
+    { "MVBAR", 15,12,0, 0,0,1, 0,0,
+      PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0},
+      NULL, NULL, vbar_write },
     { "SCTLR_EL3", 0,1,0, 3,6,0, ARM_CP_STATE_AA64,0,
       PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[3]), {0, 0},
       NULL, NULL, sctlr_write, NULL, raw_write, },
@@ -2086,29 +2102,6 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
     REGINFO_SENTINEL
 };
 
-static const ARMCPRegInfo el3_cp_reginfo[] = {
-    { "SCR_EL3", 0,1,1, 3,6,0, ARM_CP_STATE_AA64,
-      0, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.scr_el3), {0, 0},
-      NULL, NULL, scr_write },
-    { "SCR", 15,1,1, 0,0,0, 0,
-      ARM_CP_NO_MIGRATE, PL3_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0},
-      NULL, NULL, scr_write, NULL, NULL, arm_cp_reset_ignore },
-    { "SDER32_EL3", 0,1,1, 3,6,1, ARM_CP_STATE_AA64,0,
-      PL3_RW, 0, NULL, 0,
-      offsetof(CPUARMState, cp15.sder) },
-    { "SDER", 15,1,1, 0,0,1, 0,0,
-      PL3_RW, 0, NULL, 0,
-      offsetoflow32(CPUARMState, cp15.sder) },
-      /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
-    { "NSACR", 15,1,1, 0,0,2, 0,0,
-      PL3_W | PL1_R, 0, NULL, 0,
-      offsetof(CPUARMState, cp15.nsacr) },
-    { "MVBAR", 15,12,0, 0,0,1, 0,0,
-      PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0},
-      NULL, NULL, vbar_write },
-    REGINFO_SENTINEL
-};
-
 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
@@ -2626,9 +2619,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         }
     }
     if (arm_feature(env, ARM_FEATURE_EL3)) {
-        if (arm_feature(env, ARM_FEATURE_V8)) {
-            define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
-        }
         define_arm_cp_regs(cpu, el3_cp_reginfo);
     }
     if (arm_feature(env, ARM_FEATURE_MPU)) {