From c1e26c4e35e21aac45c21cb7fb4cd55c7f1232db Mon Sep 17 00:00:00 2001
From: "Emilio G. Cota" <cota@braap.org>
Date: Mon, 6 May 2019 00:46:32 -0400
Subject: [PATCH] tcg: check CF_PARALLEL instead of parallel_cpus

Thereby decoupling the resulting translated code from the current state
of the system.

The tb->cflags field is not passed to tcg generation functions. So
we add a field to TCGContext, storing there a copy of tb->cflags.

Most architectures have <= 32 registers, which results in a 4-byte hole
in TCGContext. Use this hole for the new field.

Backports commit e82d5a2460b0e176128027651ff9b104e4bdf5cc from qemu
---
 qemu/accel/tcg/translate-all.c |  1 +
 qemu/tcg/tcg-op.c              | 10 +++++-----
 qemu/tcg/tcg.h                 |  1 +
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/qemu/accel/tcg/translate-all.c b/qemu/accel/tcg/translate-all.c
index 40d2fc5b..c3123f1f 100644
--- a/qemu/accel/tcg/translate-all.c
+++ b/qemu/accel/tcg/translate-all.c
@@ -1360,6 +1360,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
     tb->cs_base = cs_base;
     tb->flags = flags;
     tb->cflags = cflags;
+    tcg_ctx->tb_cflags = cflags;
  tb_overflow:
 
 #ifdef CONFIG_PROFILER
diff --git a/qemu/tcg/tcg-op.c b/qemu/tcg/tcg-op.c
index 17b2b312..12b13b07 100644
--- a/qemu/tcg/tcg-op.c
+++ b/qemu/tcg/tcg-op.c
@@ -97,7 +97,7 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2,
 
 void tcg_gen_mb(TCGContext *ctx, TCGBar mb_type)
 {
-    if (ctx->uc->parallel_cpus) {
+    if (ctx->tb_cflags & CF_PARALLEL) {
         tcg_gen_op1(ctx, INDEX_op_mb, mb_type);
     }
 }
@@ -3064,7 +3064,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGContext *s,
 {
     memop = tcg_canonicalize_memop(memop, 0, 0);
 
-    if (!s->uc->parallel_cpus) {
+    if (!(s->tb_cflags & CF_PARALLEL)) {
         TCGv_i32 t1 = tcg_temp_new_i32(s);
         TCGv_i32 t2 = tcg_temp_new_i32(s);
 
@@ -3109,7 +3109,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGContext *s,
 {
     memop = tcg_canonicalize_memop(memop, 1, 0);
 
-    if (!s->uc->parallel_cpus) {
+    if (!(s->tb_cflags & CF_PARALLEL)) {
         TCGv_i64 t1 = tcg_temp_new_i64(s);
         TCGv_i64 t2 = tcg_temp_new_i64(s);
 
@@ -3290,7 +3290,7 @@ static void * const table_##NAME[16] = {                                \
 void tcg_gen_atomic_##NAME##_i32                                        \
     (TCGContext *s, TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \
 {                                                                       \
-    if (s->uc->parallel_cpus) {                                         \
+    if (s->tb_cflags & CF_PARALLEL) {                                   \
         do_atomic_op_i32(s, ret, addr, val, idx, memop, table_##NAME);  \
     } else {                                                            \
         do_nonatomic_op_i32(s, ret, addr, val, idx, memop, NEW,         \
@@ -3300,7 +3300,7 @@ void tcg_gen_atomic_##NAME##_i32                                        \
 void tcg_gen_atomic_##NAME##_i64                                        \
     (TCGContext *s, TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \
 {                                                                       \
-    if (s->uc->parallel_cpus) {                                         \
+    if (s->tb_cflags & CF_PARALLEL) {                                   \
         do_atomic_op_i64(s, ret, addr, val, idx, memop, table_##NAME);  \
     } else {                                                            \
         do_nonatomic_op_i64(s, ret, addr, val, idx, memop, NEW,         \
diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h
index 8ca028d9..235d4f4c 100644
--- a/qemu/tcg/tcg.h
+++ b/qemu/tcg/tcg.h
@@ -770,6 +770,7 @@ struct TCGContext {
     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
 
     TCGRegSet reserved_regs;
+    uint32_t tb_cflags; /* cflags of the current TB */
     intptr_t current_frame_offset;
     intptr_t frame_start;
     intptr_t frame_end;