diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c
index 6c0f87fa..60bf91b1 100644
--- a/qemu/target/arm/translate.c
+++ b/qemu/target/arm/translate.c
@@ -1146,7 +1146,8 @@ static long neon_full_reg_offset(unsigned reg)
     return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
 }
 
-/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
+/*
+ * Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
  * where 0 is the least significant end of the register.
  */
 static inline long
@@ -1155,7 +1156,8 @@ neon_element_offset(int reg, int element, MemOp size)
     int element_size = 1 << size;
     int ofs = element * element_size;
 #ifdef HOST_WORDS_BIGENDIAN
-    /* Calculate the offset assuming fully little-endian,
+    /*
+     * Calculate the offset assuming fully little-endian,
      * then XOR to account for the order of the 8-byte units.
      */
     if (element_size < 8) {
@@ -1180,28 +1182,18 @@ static inline long vfp_reg_offset(bool dp, unsigned reg)
     }
 }
 
-/* Return the offset of a 32-bit piece of a NEON register.
-   zero is the least significant end of the register.  */
-static inline long
-neon_reg_offset (int reg, int n)
-{
-    int sreg;
-    sreg = reg * 2 + n;
-    return vfp_reg_offset(0, sreg);
-}
-
 static TCGv_i32 neon_load_reg(DisasContext *s, int reg, int pass)
 {
     TCGContext *tcg_ctx = s->uc->tcg_ctx;
     TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
-    tcg_gen_ld_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, neon_reg_offset(reg, pass));
+    tcg_gen_ld_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, neon_element_offset(reg, pass, MO_32));
     return tmp;
 }
 
 static void neon_store_reg(DisasContext *s, int reg, int pass, TCGv_i32 var)
 {
     TCGContext *tcg_ctx = s->uc->tcg_ctx;
-    tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->cpu_env, neon_reg_offset(reg, pass));
+    tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->cpu_env, neon_element_offset(reg, pass, MO_32));
     tcg_temp_free_i32(tcg_ctx, var);
 }