From bff31d8822cbcce9ddf31c8644d8bc1825747aff Mon Sep 17 00:00:00 2001
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: Fri, 26 Feb 2021 02:23:26 -0500
Subject: [PATCH] target/riscv: implementation-defined constant parameters

vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.

Backports 32931383270e2ca8209267ca99f23f3c5f780982 from qemu
---
 qemu/target/riscv/cpu.c | 8 +++++++-
 qemu/target/riscv/cpu.h | 5 +++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c
index 94fa806f..73f379c7 100644
--- a/qemu/target/riscv/cpu.c
+++ b/qemu/target/riscv/cpu.c
@@ -98,6 +98,11 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
     env->priv_ver = priv_ver;
 }
 
+static void set_vext_version(CPURISCVState *env, int vext_ver)
+{
+    env->vext_ver = vext_ver;
+}
+
 static void set_feature(CPURISCVState *env, int feature)
 {
     env->features |= (1ULL << feature);
@@ -114,7 +119,8 @@ static void riscv_any_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
 {
     CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-set_priv_version(env, PRIV_VERSION_1_11_0);
+    set_priv_version(env, PRIV_VERSION_1_11_0);
+    set_vext_version(env, VEXT_VERSION_0_07_1);
     set_resetvec(env, DEFAULT_RSTVEC);
 }
 
diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h
index f610ff0b..9288413a 100644
--- a/qemu/target/riscv/cpu.h
+++ b/qemu/target/riscv/cpu.h
@@ -83,6 +83,8 @@ enum {
 #define PRIV_VERSION_1_10_0 0x00011000
 #define PRIV_VERSION_1_11_0 0x00011100
 
+#define VEXT_VERSION_0_07_1 0x00000701
+
 #define TRANSLATE_PMP_FAIL 2
 #define TRANSLATE_FAIL 1
 #define TRANSLATE_SUCCESS 0
@@ -118,6 +120,7 @@ struct CPURISCVState {
     target_ulong guest_phys_fault_addr;
 
     target_ulong priv_ver;
+    target_ulong vext_ver;
     target_ulong misa;
     target_ulong misa_mask;
 
@@ -279,6 +282,8 @@ typedef struct RISCVCPU {
     struct {
         bool ext_ifencei;
         bool ext_icsr;
+        uint16_t vlen;
+        uint16_t elen;
     } cfg;
 } RISCVCPU;