From be78062fd87ed1eb719af55b9a967e00a8287966 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 14 Jun 2020 21:40:58 -0400 Subject: [PATCH] tcg: Implement gvec support for rotate by vector MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No host backend support yet, but the interfaces for rotlv and rotrv are in place. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v3: Drop the generic expansion from rot to shift; we can do better for each backend, and then this code becomes unused. Backports commit 5d0ceda902915e3f0e21c39d142c92c4e97c3ebb from qemu --- qemu/aarch64.h | 12 +++ qemu/aarch64eb.h | 12 +++ qemu/accel/tcg/tcg-runtime-gvec.c | 96 +++++++++++++++++++++++ qemu/accel/tcg/tcg-runtime.h | 10 +++ qemu/arm.h | 12 +++ qemu/armeb.h | 12 +++ qemu/header_gen.py | 12 +++ qemu/m68k.h | 12 +++ qemu/mips.h | 12 +++ qemu/mips64.h | 12 +++ qemu/mips64el.h | 12 +++ qemu/mipsel.h | 12 +++ qemu/powerpc.h | 12 +++ qemu/riscv32.h | 12 +++ qemu/riscv64.h | 12 +++ qemu/sparc.h | 12 +++ qemu/sparc64.h | 12 +++ qemu/tcg/README | 4 +- qemu/tcg/aarch64/tcg-target.h | 1 + qemu/tcg/i386/tcg-target.h | 1 + qemu/tcg/tcg-op-gvec.c | 122 ++++++++++++++++++++++++++++++ qemu/tcg/tcg-op-gvec.h | 4 + qemu/tcg/tcg-op-vec.c | 10 +++ qemu/tcg/tcg-op.h | 2 + qemu/tcg/tcg-opc.h | 2 + qemu/tcg/tcg.c | 3 + qemu/tcg/tcg.h | 3 +- qemu/x86_64.h | 12 +++ 28 files changed, 448 insertions(+), 2 deletions(-) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 78ad85f7..15b1d40f 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_aarch64 #define helper_gvec_rotl32i helper_gvec_rotl32i_aarch64 #define helper_gvec_rotl64i helper_gvec_rotl64i_aarch64 +#define helper_gvec_rotl8v helper_gvec_rotl8v_aarch64 +#define helper_gvec_rotl16v helper_gvec_rotl16v_aarch64 +#define helper_gvec_rotl32v helper_gvec_rotl32v_aarch64 +#define helper_gvec_rotl64v helper_gvec_rotl64v_aarch64 +#define helper_gvec_rotr8v helper_gvec_rotr8v_aarch64 +#define helper_gvec_rotr16v helper_gvec_rotr16v_aarch64 +#define helper_gvec_rotr32v helper_gvec_rotr32v_aarch64 +#define helper_gvec_rotr64v helper_gvec_rotr64v_aarch64 #define helper_gvec_sar8i helper_gvec_sar8i_aarch64 #define helper_gvec_sar8v helper_gvec_sar8v_aarch64 #define helper_gvec_sar16i helper_gvec_sar16i_aarch64 @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_aarch64 #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_aarch64 #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_aarch64 +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_aarch64 +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_aarch64 #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_aarch64 #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_aarch64 #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_aarch64 @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_aarch64 #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_aarch64 #define tcg_gen_rotli_vec tcg_gen_rotli_vec_aarch64 +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_aarch64 #define tcg_gen_rotri_vec tcg_gen_rotri_vec_aarch64 +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_aarch64 #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_aarch64 #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_aarch64 #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 7b6fabab..62f6502d 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_aarch64eb #define helper_gvec_rotl32i helper_gvec_rotl32i_aarch64eb #define helper_gvec_rotl64i helper_gvec_rotl64i_aarch64eb +#define helper_gvec_rotl8v helper_gvec_rotl8v_aarch64eb +#define helper_gvec_rotl16v helper_gvec_rotl16v_aarch64eb +#define helper_gvec_rotl32v helper_gvec_rotl32v_aarch64eb +#define helper_gvec_rotl64v helper_gvec_rotl64v_aarch64eb +#define helper_gvec_rotr8v helper_gvec_rotr8v_aarch64eb +#define helper_gvec_rotr16v helper_gvec_rotr16v_aarch64eb +#define helper_gvec_rotr32v helper_gvec_rotr32v_aarch64eb +#define helper_gvec_rotr64v helper_gvec_rotr64v_aarch64eb #define helper_gvec_sar8i helper_gvec_sar8i_aarch64eb #define helper_gvec_sar8v helper_gvec_sar8v_aarch64eb #define helper_gvec_sar16i helper_gvec_sar16i_aarch64eb @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_aarch64eb #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_aarch64eb #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_aarch64eb +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_aarch64eb +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_aarch64eb #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_aarch64eb #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_aarch64eb #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_aarch64eb @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_aarch64eb #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_aarch64eb #define tcg_gen_rotli_vec tcg_gen_rotli_vec_aarch64eb +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_aarch64eb #define tcg_gen_rotri_vec tcg_gen_rotri_vec_aarch64eb +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_aarch64eb #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_aarch64eb #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_aarch64eb #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_aarch64eb diff --git a/qemu/accel/tcg/tcg-runtime-gvec.c b/qemu/accel/tcg/tcg-runtime-gvec.c index 5cc72fb3..0e3bdf82 100644 --- a/qemu/accel/tcg/tcg-runtime-gvec.c +++ b/qemu/accel/tcg/tcg-runtime-gvec.c @@ -913,6 +913,102 @@ void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc) clear_high(d, oprsz, desc); } +void HELPER(gvec_rotl8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { + uint8_t sh = *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) = rol8(*(uint8_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { + uint8_t sh = *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) = rol16(*(uint16_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { + uint8_t sh = *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) = rol32(*(uint32_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotl64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { + uint8_t sh = *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) = rol64(*(uint64_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { + uint8_t sh = *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) = ror8(*(uint8_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { + uint8_t sh = *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) = ror16(*(uint16_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { + uint8_t sh = *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) = ror32(*(uint32_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_rotr64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { + uint8_t sh = *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) = ror64(*(uint64_t *)(a + i), sh); + } + clear_high(d, oprsz, desc); +} + #define DO_CMP1(NAME, TYPE, OP) \ void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \ { \ diff --git a/qemu/accel/tcg/tcg-runtime.h b/qemu/accel/tcg/tcg-runtime.h index cf10c836..4eda24e6 100644 --- a/qemu/accel/tcg/tcg-runtime.h +++ b/qemu/accel/tcg/tcg-runtime.h @@ -279,6 +279,16 @@ DEF_HELPER_FLAGS_4(gvec_sar16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sar32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sar64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotl64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_rotr8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotr16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotr32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_rotr64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/qemu/arm.h b/qemu/arm.h index 8701ab19..5bf2f055 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_arm #define helper_gvec_rotl32i helper_gvec_rotl32i_arm #define helper_gvec_rotl64i helper_gvec_rotl64i_arm +#define helper_gvec_rotl8v helper_gvec_rotl8v_arm +#define helper_gvec_rotl16v helper_gvec_rotl16v_arm +#define helper_gvec_rotl32v helper_gvec_rotl32v_arm +#define helper_gvec_rotl64v helper_gvec_rotl64v_arm +#define helper_gvec_rotr8v helper_gvec_rotr8v_arm +#define helper_gvec_rotr16v helper_gvec_rotr16v_arm +#define helper_gvec_rotr32v helper_gvec_rotr32v_arm +#define helper_gvec_rotr64v helper_gvec_rotr64v_arm #define helper_gvec_sar8i helper_gvec_sar8i_arm #define helper_gvec_sar8v helper_gvec_sar8v_arm #define helper_gvec_sar16i helper_gvec_sar16i_arm @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_arm #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_arm #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_arm +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_arm +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_arm #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_arm #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_arm #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_arm @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_arm #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_arm #define tcg_gen_rotli_vec tcg_gen_rotli_vec_arm +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_arm #define tcg_gen_rotri_vec tcg_gen_rotri_vec_arm +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_arm #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_arm #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_arm #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index d368bf6b..d2080cc3 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_armeb #define helper_gvec_rotl32i helper_gvec_rotl32i_armeb #define helper_gvec_rotl64i helper_gvec_rotl64i_armeb +#define helper_gvec_rotl8v helper_gvec_rotl8v_armeb +#define helper_gvec_rotl16v helper_gvec_rotl16v_armeb +#define helper_gvec_rotl32v helper_gvec_rotl32v_armeb +#define helper_gvec_rotl64v helper_gvec_rotl64v_armeb +#define helper_gvec_rotr8v helper_gvec_rotr8v_armeb +#define helper_gvec_rotr16v helper_gvec_rotr16v_armeb +#define helper_gvec_rotr32v helper_gvec_rotr32v_armeb +#define helper_gvec_rotr64v helper_gvec_rotr64v_armeb #define helper_gvec_sar8i helper_gvec_sar8i_armeb #define helper_gvec_sar8v helper_gvec_sar8v_armeb #define helper_gvec_sar16i helper_gvec_sar16i_armeb @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_armeb #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_armeb #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_armeb +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_armeb +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_armeb #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_armeb #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_armeb #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_armeb @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_armeb #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_armeb #define tcg_gen_rotli_vec tcg_gen_rotli_vec_armeb +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_armeb #define tcg_gen_rotri_vec tcg_gen_rotri_vec_armeb +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_armeb #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_armeb #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_armeb #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 187a3009..c962309c 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -1244,6 +1244,14 @@ symbols = ( 'helper_gvec_rotl16i', 'helper_gvec_rotl32i', 'helper_gvec_rotl64i', + 'helper_gvec_rotl8v', + 'helper_gvec_rotl16v', + 'helper_gvec_rotl32v', + 'helper_gvec_rotl64v', + 'helper_gvec_rotr8v', + 'helper_gvec_rotr16v', + 'helper_gvec_rotr32v', + 'helper_gvec_rotr64v', 'helper_gvec_sar8i', 'helper_gvec_sar8v', 'helper_gvec_sar16i', @@ -2916,6 +2924,8 @@ symbols = ( 'tcg_gen_gvec_ors', 'tcg_gen_gvec_rotli', 'tcg_gen_gvec_rotri', + 'tcg_gen_gvec_rotlv', + 'tcg_gen_gvec_rotrv', 'tcg_gen_gvec_sar8v', 'tcg_gen_gvec_sar16v', 'tcg_gen_gvec_sar32v', @@ -3040,7 +3050,9 @@ symbols = ( 'tcg_gen_rotli_i32', 'tcg_gen_rotli_i64', 'tcg_gen_rotli_vec', + 'tcg_gen_rotlv_vec', 'tcg_gen_rotri_vec', + 'tcg_gen_rotrv_vec', 'tcg_gen_rotr_i32', 'tcg_gen_rotr_i64', 'tcg_gen_rotri_i32', diff --git a/qemu/m68k.h b/qemu/m68k.h index 4ec08eba..92be9023 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_m68k #define helper_gvec_rotl32i helper_gvec_rotl32i_m68k #define helper_gvec_rotl64i helper_gvec_rotl64i_m68k +#define helper_gvec_rotl8v helper_gvec_rotl8v_m68k +#define helper_gvec_rotl16v helper_gvec_rotl16v_m68k +#define helper_gvec_rotl32v helper_gvec_rotl32v_m68k +#define helper_gvec_rotl64v helper_gvec_rotl64v_m68k +#define helper_gvec_rotr8v helper_gvec_rotr8v_m68k +#define helper_gvec_rotr16v helper_gvec_rotr16v_m68k +#define helper_gvec_rotr32v helper_gvec_rotr32v_m68k +#define helper_gvec_rotr64v helper_gvec_rotr64v_m68k #define helper_gvec_sar8i helper_gvec_sar8i_m68k #define helper_gvec_sar8v helper_gvec_sar8v_m68k #define helper_gvec_sar16i helper_gvec_sar16i_m68k @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_m68k #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_m68k #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_m68k +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_m68k +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_m68k #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_m68k #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_m68k #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_m68k @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_m68k #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_m68k #define tcg_gen_rotli_vec tcg_gen_rotli_vec_m68k +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_m68k #define tcg_gen_rotri_vec tcg_gen_rotri_vec_m68k +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_m68k #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_m68k #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_m68k #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_m68k diff --git a/qemu/mips.h b/qemu/mips.h index 58938ca4..39a840ef 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_mips #define helper_gvec_rotl32i helper_gvec_rotl32i_mips #define helper_gvec_rotl64i helper_gvec_rotl64i_mips +#define helper_gvec_rotl8v helper_gvec_rotl8v_mips +#define helper_gvec_rotl16v helper_gvec_rotl16v_mips +#define helper_gvec_rotl32v helper_gvec_rotl32v_mips +#define helper_gvec_rotl64v helper_gvec_rotl64v_mips +#define helper_gvec_rotr8v helper_gvec_rotr8v_mips +#define helper_gvec_rotr16v helper_gvec_rotr16v_mips +#define helper_gvec_rotr32v helper_gvec_rotr32v_mips +#define helper_gvec_rotr64v helper_gvec_rotr64v_mips #define helper_gvec_sar8i helper_gvec_sar8i_mips #define helper_gvec_sar8v helper_gvec_sar8v_mips #define helper_gvec_sar16i helper_gvec_sar16i_mips @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_mips #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_mips #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_mips +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_mips +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_mips #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mips #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mips #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips #define tcg_gen_rotli_vec tcg_gen_rotli_vec_mips +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_mips #define tcg_gen_rotri_vec tcg_gen_rotri_vec_mips +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_mips #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index a2d27419..1188d368 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_mips64 #define helper_gvec_rotl32i helper_gvec_rotl32i_mips64 #define helper_gvec_rotl64i helper_gvec_rotl64i_mips64 +#define helper_gvec_rotl8v helper_gvec_rotl8v_mips64 +#define helper_gvec_rotl16v helper_gvec_rotl16v_mips64 +#define helper_gvec_rotl32v helper_gvec_rotl32v_mips64 +#define helper_gvec_rotl64v helper_gvec_rotl64v_mips64 +#define helper_gvec_rotr8v helper_gvec_rotr8v_mips64 +#define helper_gvec_rotr16v helper_gvec_rotr16v_mips64 +#define helper_gvec_rotr32v helper_gvec_rotr32v_mips64 +#define helper_gvec_rotr64v helper_gvec_rotr64v_mips64 #define helper_gvec_sar8i helper_gvec_sar8i_mips64 #define helper_gvec_sar8v helper_gvec_sar8v_mips64 #define helper_gvec_sar16i helper_gvec_sar16i_mips64 @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_mips64 #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_mips64 #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_mips64 +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_mips64 +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_mips64 #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mips64 #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mips64 #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips64 @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips64 #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips64 #define tcg_gen_rotli_vec tcg_gen_rotli_vec_mips64 +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_mips64 #define tcg_gen_rotri_vec tcg_gen_rotri_vec_mips64 +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_mips64 #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips64 #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips64 #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 6cbf764d..325fc644 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_mips64el #define helper_gvec_rotl32i helper_gvec_rotl32i_mips64el #define helper_gvec_rotl64i helper_gvec_rotl64i_mips64el +#define helper_gvec_rotl8v helper_gvec_rotl8v_mips64el +#define helper_gvec_rotl16v helper_gvec_rotl16v_mips64el +#define helper_gvec_rotl32v helper_gvec_rotl32v_mips64el +#define helper_gvec_rotl64v helper_gvec_rotl64v_mips64el +#define helper_gvec_rotr8v helper_gvec_rotr8v_mips64el +#define helper_gvec_rotr16v helper_gvec_rotr16v_mips64el +#define helper_gvec_rotr32v helper_gvec_rotr32v_mips64el +#define helper_gvec_rotr64v helper_gvec_rotr64v_mips64el #define helper_gvec_sar8i helper_gvec_sar8i_mips64el #define helper_gvec_sar8v helper_gvec_sar8v_mips64el #define helper_gvec_sar16i helper_gvec_sar16i_mips64el @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_mips64el #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_mips64el #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_mips64el +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_mips64el +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_mips64el #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mips64el #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mips64el #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips64el @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips64el #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips64el #define tcg_gen_rotli_vec tcg_gen_rotli_vec_mips64el +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_mips64el #define tcg_gen_rotri_vec tcg_gen_rotri_vec_mips64el +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_mips64el #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips64el #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips64el #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index d71f3d85..d339cfac 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_mipsel #define helper_gvec_rotl32i helper_gvec_rotl32i_mipsel #define helper_gvec_rotl64i helper_gvec_rotl64i_mipsel +#define helper_gvec_rotl8v helper_gvec_rotl8v_mipsel +#define helper_gvec_rotl16v helper_gvec_rotl16v_mipsel +#define helper_gvec_rotl32v helper_gvec_rotl32v_mipsel +#define helper_gvec_rotl64v helper_gvec_rotl64v_mipsel +#define helper_gvec_rotr8v helper_gvec_rotr8v_mipsel +#define helper_gvec_rotr16v helper_gvec_rotr16v_mipsel +#define helper_gvec_rotr32v helper_gvec_rotr32v_mipsel +#define helper_gvec_rotr64v helper_gvec_rotr64v_mipsel #define helper_gvec_sar8i helper_gvec_sar8i_mipsel #define helper_gvec_sar8v helper_gvec_sar8v_mipsel #define helper_gvec_sar16i helper_gvec_sar16i_mipsel @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_mipsel #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_mipsel #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_mipsel +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_mipsel +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_mipsel #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mipsel #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mipsel #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mipsel @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mipsel #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mipsel #define tcg_gen_rotli_vec tcg_gen_rotli_vec_mipsel +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_mipsel #define tcg_gen_rotri_vec tcg_gen_rotri_vec_mipsel +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_mipsel #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mipsel #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mipsel #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index 11a3d3c1..d51feb07 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_powerpc #define helper_gvec_rotl32i helper_gvec_rotl32i_powerpc #define helper_gvec_rotl64i helper_gvec_rotl64i_powerpc +#define helper_gvec_rotl8v helper_gvec_rotl8v_powerpc +#define helper_gvec_rotl16v helper_gvec_rotl16v_powerpc +#define helper_gvec_rotl32v helper_gvec_rotl32v_powerpc +#define helper_gvec_rotl64v helper_gvec_rotl64v_powerpc +#define helper_gvec_rotr8v helper_gvec_rotr8v_powerpc +#define helper_gvec_rotr16v helper_gvec_rotr16v_powerpc +#define helper_gvec_rotr32v helper_gvec_rotr32v_powerpc +#define helper_gvec_rotr64v helper_gvec_rotr64v_powerpc #define helper_gvec_sar8i helper_gvec_sar8i_powerpc #define helper_gvec_sar8v helper_gvec_sar8v_powerpc #define helper_gvec_sar16i helper_gvec_sar16i_powerpc @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_powerpc #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_powerpc #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_powerpc +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_powerpc +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_powerpc #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_powerpc #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_powerpc #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_powerpc @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_powerpc #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_powerpc #define tcg_gen_rotli_vec tcg_gen_rotli_vec_powerpc +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_powerpc #define tcg_gen_rotri_vec tcg_gen_rotri_vec_powerpc +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_powerpc #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_powerpc #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_powerpc #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_powerpc diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 1f8cc376..cf247d42 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_riscv32 #define helper_gvec_rotl32i helper_gvec_rotl32i_riscv32 #define helper_gvec_rotl64i helper_gvec_rotl64i_riscv32 +#define helper_gvec_rotl8v helper_gvec_rotl8v_riscv32 +#define helper_gvec_rotl16v helper_gvec_rotl16v_riscv32 +#define helper_gvec_rotl32v helper_gvec_rotl32v_riscv32 +#define helper_gvec_rotl64v helper_gvec_rotl64v_riscv32 +#define helper_gvec_rotr8v helper_gvec_rotr8v_riscv32 +#define helper_gvec_rotr16v helper_gvec_rotr16v_riscv32 +#define helper_gvec_rotr32v helper_gvec_rotr32v_riscv32 +#define helper_gvec_rotr64v helper_gvec_rotr64v_riscv32 #define helper_gvec_sar8i helper_gvec_sar8i_riscv32 #define helper_gvec_sar8v helper_gvec_sar8v_riscv32 #define helper_gvec_sar16i helper_gvec_sar16i_riscv32 @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_riscv32 #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_riscv32 #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_riscv32 +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_riscv32 +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_riscv32 #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_riscv32 #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_riscv32 #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_riscv32 @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_riscv32 #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_riscv32 #define tcg_gen_rotli_vec tcg_gen_rotli_vec_riscv32 +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_riscv32 #define tcg_gen_rotri_vec tcg_gen_rotri_vec_riscv32 +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_riscv32 #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_riscv32 #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_riscv32 #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 47e90bd3..e29c2282 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_riscv64 #define helper_gvec_rotl32i helper_gvec_rotl32i_riscv64 #define helper_gvec_rotl64i helper_gvec_rotl64i_riscv64 +#define helper_gvec_rotl8v helper_gvec_rotl8v_riscv64 +#define helper_gvec_rotl16v helper_gvec_rotl16v_riscv64 +#define helper_gvec_rotl32v helper_gvec_rotl32v_riscv64 +#define helper_gvec_rotl64v helper_gvec_rotl64v_riscv64 +#define helper_gvec_rotr8v helper_gvec_rotr8v_riscv64 +#define helper_gvec_rotr16v helper_gvec_rotr16v_riscv64 +#define helper_gvec_rotr32v helper_gvec_rotr32v_riscv64 +#define helper_gvec_rotr64v helper_gvec_rotr64v_riscv64 #define helper_gvec_sar8i helper_gvec_sar8i_riscv64 #define helper_gvec_sar8v helper_gvec_sar8v_riscv64 #define helper_gvec_sar16i helper_gvec_sar16i_riscv64 @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_riscv64 #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_riscv64 #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_riscv64 +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_riscv64 +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_riscv64 #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_riscv64 #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_riscv64 #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_riscv64 @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_riscv64 #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_riscv64 #define tcg_gen_rotli_vec tcg_gen_rotli_vec_riscv64 +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_riscv64 #define tcg_gen_rotri_vec tcg_gen_rotri_vec_riscv64 +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_riscv64 #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_riscv64 #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_riscv64 #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_riscv64 diff --git a/qemu/sparc.h b/qemu/sparc.h index 3c0ca70f..add85e0e 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_sparc #define helper_gvec_rotl32i helper_gvec_rotl32i_sparc #define helper_gvec_rotl64i helper_gvec_rotl64i_sparc +#define helper_gvec_rotl8v helper_gvec_rotl8v_sparc +#define helper_gvec_rotl16v helper_gvec_rotl16v_sparc +#define helper_gvec_rotl32v helper_gvec_rotl32v_sparc +#define helper_gvec_rotl64v helper_gvec_rotl64v_sparc +#define helper_gvec_rotr8v helper_gvec_rotr8v_sparc +#define helper_gvec_rotr16v helper_gvec_rotr16v_sparc +#define helper_gvec_rotr32v helper_gvec_rotr32v_sparc +#define helper_gvec_rotr64v helper_gvec_rotr64v_sparc #define helper_gvec_sar8i helper_gvec_sar8i_sparc #define helper_gvec_sar8v helper_gvec_sar8v_sparc #define helper_gvec_sar16i helper_gvec_sar16i_sparc @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_sparc #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_sparc #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_sparc +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_sparc +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_sparc #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_sparc #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_sparc #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_sparc @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_sparc #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_sparc #define tcg_gen_rotli_vec tcg_gen_rotli_vec_sparc +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_sparc #define tcg_gen_rotri_vec tcg_gen_rotri_vec_sparc +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_sparc #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_sparc #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_sparc #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index e4864dfe..e397d29d 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_sparc64 #define helper_gvec_rotl32i helper_gvec_rotl32i_sparc64 #define helper_gvec_rotl64i helper_gvec_rotl64i_sparc64 +#define helper_gvec_rotl8v helper_gvec_rotl8v_sparc64 +#define helper_gvec_rotl16v helper_gvec_rotl16v_sparc64 +#define helper_gvec_rotl32v helper_gvec_rotl32v_sparc64 +#define helper_gvec_rotl64v helper_gvec_rotl64v_sparc64 +#define helper_gvec_rotr8v helper_gvec_rotr8v_sparc64 +#define helper_gvec_rotr16v helper_gvec_rotr16v_sparc64 +#define helper_gvec_rotr32v helper_gvec_rotr32v_sparc64 +#define helper_gvec_rotr64v helper_gvec_rotr64v_sparc64 #define helper_gvec_sar8i helper_gvec_sar8i_sparc64 #define helper_gvec_sar8v helper_gvec_sar8v_sparc64 #define helper_gvec_sar16i helper_gvec_sar16i_sparc64 @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_sparc64 #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_sparc64 #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_sparc64 +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_sparc64 +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_sparc64 #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_sparc64 #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_sparc64 #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_sparc64 @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_sparc64 #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_sparc64 #define tcg_gen_rotli_vec tcg_gen_rotli_vec_sparc64 +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_sparc64 #define tcg_gen_rotri_vec tcg_gen_rotri_vec_sparc64 +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_sparc64 #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_sparc64 #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_sparc64 #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_sparc64 diff --git a/qemu/tcg/README b/qemu/tcg/README index 26d45f2f..27d07d9f 100644 --- a/qemu/tcg/README +++ b/qemu/tcg/README @@ -616,8 +616,10 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32. * shrv_vec v0, v1, v2 * sarv_vec v0, v1, v2 +* rotlv_vec v0, v1, v2 +* rotrv_vec v0, v1, v2 - Similarly for logical and arithmetic right shift. + Similarly for logical and arithmetic right shift, and rotates. * cmp_vec v0, v1, v2, cond diff --git a/qemu/tcg/aarch64/tcg-target.h b/qemu/tcg/aarch64/tcg-target.h index 225a597f..a5477bbc 100644 --- a/qemu/tcg/aarch64/tcg-target.h +++ b/qemu/tcg/aarch64/tcg-target.h @@ -134,6 +134,7 @@ typedef enum { #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 1 diff --git a/qemu/tcg/i386/tcg-target.h b/qemu/tcg/i386/tcg-target.h index 77e1ec50..8481b1c7 100644 --- a/qemu/tcg/i386/tcg-target.h +++ b/qemu/tcg/i386/tcg-target.h @@ -217,6 +217,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shv_vec have_avx2 diff --git a/qemu/tcg/tcg-op-gvec.c b/qemu/tcg/tcg-op-gvec.c index 0465bcfb..7f814d1b 100644 --- a/qemu/tcg/tcg-op-gvec.c +++ b/qemu/tcg/tcg-op-gvec.c @@ -3172,6 +3172,128 @@ void tcg_gen_gvec_sarv(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aof tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } +/* + * Similarly for rotates. + */ + +static void tcg_gen_rotlv_mod_vec(TCGContext *s, unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t = tcg_temp_new_vec_matching(s, d); + + tcg_gen_dupi_vec(s, vece, t, (8 << vece) - 1); + tcg_gen_and_vec(s, vece, t, t, b); + tcg_gen_rotlv_vec(s, vece, d, a, t); + tcg_temp_free_vec(s, t); +} + +static void tcg_gen_rotl_mod_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t = tcg_temp_new_i32(s); + + tcg_gen_andi_i32(s, t, b, 31); + tcg_gen_rotl_i32(s, d, a, t); + tcg_temp_free_i32(s, t); +} + +static void tcg_gen_rotl_mod_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t = tcg_temp_new_i64(s); + + tcg_gen_andi_i64(s, t, b, 63); + tcg_gen_rotl_i64(s, d, a, t); + tcg_temp_free_i64(s, t); +} + +void tcg_gen_gvec_rotlv(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] = { INDEX_op_rotlv_vec, 0 }; + static const GVecGen3 g[4] = { + { .fniv = tcg_gen_rotlv_mod_vec, + .fno = gen_helper_gvec_rotl8v, + .opt_opc = vecop_list, + .vece = MO_8 }, + { .fniv = tcg_gen_rotlv_mod_vec, + .fno = gen_helper_gvec_rotl16v, + .opt_opc = vecop_list, + .vece = MO_16 }, + { .fni4 = tcg_gen_rotl_mod_i32, + .fniv = tcg_gen_rotlv_mod_vec, + .fno = gen_helper_gvec_rotl32v, + .opt_opc = vecop_list, + .vece = MO_32 }, + { .fni8 = tcg_gen_rotl_mod_i64, + .fniv = tcg_gen_rotlv_mod_vec, + .fno = gen_helper_gvec_rotl64v, + .opt_opc = vecop_list, + .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .vece = MO_64 }, + }; + + tcg_debug_assert(vece <= MO_64); + tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +static void tcg_gen_rotrv_mod_vec(TCGContext *s, unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t = tcg_temp_new_vec_matching(s, d); + + tcg_gen_dupi_vec(s, vece, t, (8 << vece) - 1); + tcg_gen_and_vec(s, vece, t, t, b); + tcg_gen_rotrv_vec(s, vece, d, a, t); + tcg_temp_free_vec(s, t); +} + +static void tcg_gen_rotr_mod_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t = tcg_temp_new_i32(s); + + tcg_gen_andi_i32(s, t, b, 31); + tcg_gen_rotr_i32(s, d, a, t); + tcg_temp_free_i32(s, t); +} + +static void tcg_gen_rotr_mod_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t = tcg_temp_new_i64(s); + + tcg_gen_andi_i64(s, t, b, 63); + tcg_gen_rotr_i64(s, d, a, t); + tcg_temp_free_i64(s, t); +} + +void tcg_gen_gvec_rotrv(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] = { INDEX_op_rotrv_vec, 0 }; + static const GVecGen3 g[4] = { + { .fniv = tcg_gen_rotrv_mod_vec, + .fno = gen_helper_gvec_rotr8v, + .opt_opc = vecop_list, + .vece = MO_8 }, + { .fniv = tcg_gen_rotrv_mod_vec, + .fno = gen_helper_gvec_rotr16v, + .opt_opc = vecop_list, + .vece = MO_16 }, + { .fni4 = tcg_gen_rotr_mod_i32, + .fniv = tcg_gen_rotrv_mod_vec, + .fno = gen_helper_gvec_rotr32v, + .opt_opc = vecop_list, + .vece = MO_32 }, + { .fni8 = tcg_gen_rotr_mod_i64, + .fniv = tcg_gen_rotrv_mod_vec, + .fno = gen_helper_gvec_rotr64v, + .opt_opc = vecop_list, + .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .vece = MO_64 }, + }; + + tcg_debug_assert(vece <= MO_64); + tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + /* Expand OPSZ bytes worth of three-operand operations using i32 elements. */ static void expand_cmp_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, TCGCond cond) diff --git a/qemu/tcg/tcg-op-gvec.h b/qemu/tcg/tcg-op-gvec.h index 148f51d4..f1ea724f 100644 --- a/qemu/tcg/tcg-op-gvec.h +++ b/qemu/tcg/tcg-op-gvec.h @@ -356,6 +356,10 @@ void tcg_gen_gvec_shrv(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sarv(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotlv(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotrv(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_cmp(TCGContext *s, TCGCond cond, unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, diff --git a/qemu/tcg/tcg-op-vec.c b/qemu/tcg/tcg-op-vec.c index 24287d71..d5e64c7e 100644 --- a/qemu/tcg/tcg-op-vec.c +++ b/qemu/tcg/tcg-op-vec.c @@ -698,6 +698,16 @@ void tcg_gen_sarv_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv do_op3_nofail(s, vece, r, a, b, INDEX_op_sarv_vec); } +void tcg_gen_rotlv_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3_nofail(s, vece, r, a, b, INDEX_op_rotlv_vec); +} + +void tcg_gen_rotrv_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3_nofail(s, vece, r, a, b, INDEX_op_rotrv_vec); +} + static void do_shifts(TCGContext *tcg_ctx, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v) { diff --git a/qemu/tcg/tcg-op.h b/qemu/tcg/tcg-op.h index aac2bfc1..84bdabbe 100644 --- a/qemu/tcg/tcg-op.h +++ b/qemu/tcg/tcg-op.h @@ -1011,6 +1011,8 @@ void tcg_gen_sars_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_ void tcg_gen_shlv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_shrv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_sarv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_rotlv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_rotrv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_cmp_vec(TCGContext *, TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); diff --git a/qemu/tcg/tcg-opc.h b/qemu/tcg/tcg-opc.h index 238693d0..4eeb5129 100644 --- a/qemu/tcg/tcg-opc.h +++ b/qemu/tcg/tcg-opc.h @@ -254,6 +254,8 @@ DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) +DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) +DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) DEF(cmp_vec, 1, 2, 1, IMPLVEC) diff --git a/qemu/tcg/tcg.c b/qemu/tcg/tcg.c index fc0ad1fb..1f4087fd 100644 --- a/qemu/tcg/tcg.c +++ b/qemu/tcg/tcg.c @@ -1080,6 +1080,9 @@ bool tcg_op_supported(TCGOpcode op) return have_vec && TCG_TARGET_HAS_shv_vec; case INDEX_op_rotli_vec: return have_vec && TCG_TARGET_HAS_roti_vec; + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + return have_vec && TCG_TARGET_HAS_rotv_vec; case INDEX_op_ssadd_vec: case INDEX_op_usadd_vec: case INDEX_op_sssub_vec: diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h index 8af05b97..24cbeffa 100644 --- a/qemu/tcg/tcg.h +++ b/qemu/tcg/tcg.h @@ -186,6 +186,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 @@ -1092,7 +1093,7 @@ static inline TCGv_ptr tcg_temp_local_new_ptr(TCGContext *s) } // UNICORN: Added -#define TCG_OP_DEFS_TABLE_SIZE 186 +#define TCG_OP_DEFS_TABLE_SIZE 188 extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE]; typedef struct TCGTargetOpDef { diff --git a/qemu/x86_64.h b/qemu/x86_64.h index 3f99f67e..937ae0e4 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -1238,6 +1238,14 @@ #define helper_gvec_rotl16i helper_gvec_rotl16i_x86_64 #define helper_gvec_rotl32i helper_gvec_rotl32i_x86_64 #define helper_gvec_rotl64i helper_gvec_rotl64i_x86_64 +#define helper_gvec_rotl8v helper_gvec_rotl8v_x86_64 +#define helper_gvec_rotl16v helper_gvec_rotl16v_x86_64 +#define helper_gvec_rotl32v helper_gvec_rotl32v_x86_64 +#define helper_gvec_rotl64v helper_gvec_rotl64v_x86_64 +#define helper_gvec_rotr8v helper_gvec_rotr8v_x86_64 +#define helper_gvec_rotr16v helper_gvec_rotr16v_x86_64 +#define helper_gvec_rotr32v helper_gvec_rotr32v_x86_64 +#define helper_gvec_rotr64v helper_gvec_rotr64v_x86_64 #define helper_gvec_sar8i helper_gvec_sar8i_x86_64 #define helper_gvec_sar8v helper_gvec_sar8v_x86_64 #define helper_gvec_sar16i helper_gvec_sar16i_x86_64 @@ -2910,6 +2918,8 @@ #define tcg_gen_gvec_ors tcg_gen_gvec_ors_x86_64 #define tcg_gen_gvec_rotli tcg_gen_gvec_rotli_x86_64 #define tcg_gen_gvec_rotri tcg_gen_gvec_rotri_x86_64 +#define tcg_gen_gvec_rotlv tcg_gen_gvec_rotlv_x86_64 +#define tcg_gen_gvec_rotrv tcg_gen_gvec_rotrv_x86_64 #define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_x86_64 #define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_x86_64 #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_x86_64 @@ -3034,7 +3044,9 @@ #define tcg_gen_rotli_i32 tcg_gen_rotli_i32_x86_64 #define tcg_gen_rotli_i64 tcg_gen_rotli_i64_x86_64 #define tcg_gen_rotli_vec tcg_gen_rotli_vec_x86_64 +#define tcg_gen_rotlv_vec tcg_gen_rotlv_vec_x86_64 #define tcg_gen_rotri_vec tcg_gen_rotri_vec_x86_64 +#define tcg_gen_rotrv_vec tcg_gen_rotrv_vec_x86_64 #define tcg_gen_rotr_i32 tcg_gen_rotr_i32_x86_64 #define tcg_gen_rotr_i64 tcg_gen_rotr_i64_x86_64 #define tcg_gen_rotri_i32 tcg_gen_rotri_i32_x86_64