From bd3e9ebaeaec97d25d3dbcd7b1124031ef9ff204 Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng@gmail.com>
Date: Tue, 19 Mar 2019 23:56:43 -0400
Subject: [PATCH] RISC-V: linux-user support for RVE ABI

This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.

Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.

Backports relevant parts of 5836c3eccedb6dfab16b8f606f2de24b8938b69c
from qemu
---
 qemu/target/riscv/cpu.h      | 4 ++++
 qemu/target/riscv/cpu_user.h | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h
index 45a3721f..e5122665 100644
--- a/qemu/target/riscv/cpu.h
+++ b/qemu/target/riscv/cpu.h
@@ -125,6 +125,10 @@ struct CPURISCVState {
 
     uint32_t features;
 
+#ifdef CONFIG_USER_ONLY
+    uint32_t elf_flags;
+#endif
+
 #ifndef CONFIG_USER_ONLY
     target_ulong priv;
     target_ulong resetvec;
diff --git a/qemu/target/riscv/cpu_user.h b/qemu/target/riscv/cpu_user.h
index c2199610..52d380aa 100644
--- a/qemu/target/riscv/cpu_user.h
+++ b/qemu/target/riscv/cpu_user.h
@@ -10,4 +10,5 @@
 #define xA4 14
 #define xA5 15
 #define xA6 16
-#define xA7 17  /* syscall number goes here */
+#define xA7 17  /* syscall number for RVI ABI */
+#define xT0 5   /* syscall number for RVE ABI */