From bc434da124820798cd924525df10c1220beffc0a Mon Sep 17 00:00:00 2001
From: Leon Alrae <leon.alrae@imgtec.com>
Date: Sun, 25 Feb 2018 21:02:25 -0500
Subject: [PATCH] target-mips: fix EntryHi.EHINV being cleared on TLB exception

While implementing TLB invalidation feature we forgot to modify
part of code responsible for updating EntryHi during TLB exception.
Consequently EntryHi.EHINV is unexpectedly cleared on the exception.

Backports commit 701074a6fc7470d0ed54e4a4bcd4d491ad8da22e from qemu
---
 qemu/target-mips/helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qemu/target-mips/helper.c b/qemu/target-mips/helper.c
index c1b4b02b..f657e91c 100644
--- a/qemu/target-mips/helper.c
+++ b/qemu/target-mips/helper.c
@@ -386,6 +386,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
                        ((address >> 9) & 0x007ffff0);
     env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
+                       (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
                        (address & (TARGET_PAGE_MASK << 1));
 #if defined(TARGET_MIPS64)
     env->CP0_EntryHi &= env->SEGMask;