From ba4dcc8c2fba3e6e53abee4bbfbd38b09af0d287 Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Sun, 25 Feb 2018 03:48:08 -0500
Subject: [PATCH] target-mips: change ASID type to hold more than 8 bits

ASID currently has uint8_t type which is too small since some processors
support more than 8 bits ASID. Therefore change its type to uint16_t.

Backports commit 2d72e7b047d800c9f99262466f65a98684ecca14 from qemu
---
 qemu/target-mips/cpu.h       | 2 +-
 qemu/target-mips/helper.c    | 4 ++--
 qemu/target-mips/op_helper.c | 8 ++++----
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/qemu/target-mips/cpu.h b/qemu/target-mips/cpu.h
index 1719120e..150564c0 100644
--- a/qemu/target-mips/cpu.h
+++ b/qemu/target-mips/cpu.h
@@ -20,7 +20,7 @@ typedef struct r4k_tlb_t r4k_tlb_t;
 struct r4k_tlb_t {
     target_ulong VPN;
     uint32_t PageMask;
-    uint8_t ASID;
+    uint16_t ASID;
     uint16_t G:1;
     uint16_t C0:3;
     uint16_t C1:3;
diff --git a/qemu/target-mips/helper.c b/qemu/target-mips/helper.c
index 68a4fb68..c1b4b02b 100644
--- a/qemu/target-mips/helper.c
+++ b/qemu/target-mips/helper.c
@@ -67,7 +67,7 @@ int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
                      target_ulong address, int rw, int access_type)
 {
-    uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
+    uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
     int i;
 
     for (i = 0; i < env->tlb->tlb_in_use; i++) {
@@ -887,7 +887,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
     r4k_tlb_t *tlb;
     target_ulong addr;
     target_ulong end;
-    uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
+    uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
     target_ulong mask;
 
     tlb = &env->tlb->mmu.r4k.tlb[idx];
diff --git a/qemu/target-mips/op_helper.c b/qemu/target-mips/op_helper.c
index 6cf09627..0d00b39c 100644
--- a/qemu/target-mips/op_helper.c
+++ b/qemu/target-mips/op_helper.c
@@ -2002,7 +2002,7 @@ void r4k_helper_tlbinv(CPUMIPSState *env)
 {
     int idx;
     r4k_tlb_t *tlb;
-    uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
+    uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
 
     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
         tlb = &env->tlb->mmu.r4k.tlb[idx];
@@ -2028,7 +2028,7 @@ void r4k_helper_tlbwi(CPUMIPSState *env)
     r4k_tlb_t *tlb;
     int idx;
     target_ulong VPN;
-    uint8_t ASID;
+    uint16_t ASID;
     bool G, V0, D0, V1, D1;
 
     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
@@ -2070,7 +2070,7 @@ void r4k_helper_tlbp(CPUMIPSState *env)
     target_ulong mask;
     target_ulong tag;
     target_ulong VPN;
-    uint8_t ASID;
+    uint16_t ASID;
     int i;
 
     ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
@@ -2125,7 +2125,7 @@ static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
 void r4k_helper_tlbr(CPUMIPSState *env)
 {
     r4k_tlb_t *tlb;
-    uint8_t ASID;
+    uint16_t ASID;
     int idx;
 
     ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;