From b9df4e0ca0eecf8ab5607d007ec40597e9a2f0b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Llu=C3=ADs=20Vilanova?= Date: Sun, 4 Mar 2018 19:24:42 -0500 Subject: [PATCH] target/arm: [tcg] Port to insn_start Incrementally paves the way towards using the generic instruction translation loop. Backports commit f62bd897e64c6fb1f93e8795e835980516fe53b5 from qemu --- qemu/target/arm/translate.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index 2ead3641..031ac96c 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -12146,6 +12146,17 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) } } +static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + TCGContext *tcg_ctx = cpu->uc->tcg_ctx; + + dc->insn_start_idx = tcg_op_buf_count(tcg_ctx); + tcg_gen_insn_start(tcg_ctx, dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -12211,10 +12222,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) do { dc->base.num_insns++; - dc->insn_start_idx = tcg_op_buf_count(tcg_ctx); - tcg_gen_insn_start(tcg_ctx, dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), - 0); + arm_tr_insn_start(&dc->base, cs); if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp;