From b732ad9ebacdc61ba857668260c91e7f55eba20b Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Tue, 14 Jan 2020 07:00:55 -0500 Subject: [PATCH] tcg: Check for watchpoints in probe_write() Let size > 0 indicate a promise to write to those bytes. Check for write watchpoints in the probed range. Backports commit 03a981893c99faba84bb373976796ad7dce0aecc from qemu --- qemu/accel/tcg/cputlb.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/qemu/accel/tcg/cputlb.c b/qemu/accel/tcg/cputlb.c index 539dbb42..54bf1920 100644 --- a/qemu/accel/tcg/cputlb.c +++ b/qemu/accel/tcg/cputlb.c @@ -714,13 +714,24 @@ void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, { uintptr_t index = tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr = tlb_addr_write(entry); - if (!tlb_hit(tlb_addr_write(entry), addr)) { - /* TLB entry is for a different page */ + if (unlikely(!tlb_hit(tlb_addr, addr))) { if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); + /* TLB resize via tlb_fill may have moved the entry. */ + index = tlb_index(env, mmu_idx, addr); + entry = tlb_entry(env, mmu_idx, addr); } + tlb_addr = tlb_addr_write(entry); + } + + /* Handle watchpoints. */ + if ((tlb_addr & TLB_WATCHPOINT) && size > 0) { + cpu_check_watchpoint(env_cpu(env), addr, size, + env->iotlb[mmu_idx][index].attrs, + BP_MEM_WRITE, retaddr); } }