From b59c9c0e2cc3ba23ea28a7ebdff81f176bd58031 Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Sat, 17 Feb 2018 14:30:18 -0500 Subject: [PATCH] target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6 Implement the relationship between CP0.Status.KX, SX and UX. It should not be possible to set UX bit if SX is 0, the same applies for setting SX if KX is 0. Backports commit 2dcf7908d9e0274c08911400beb7ed14276bb170 from qemu --- qemu/target-mips/cpu.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/qemu/target-mips/cpu.h b/qemu/target-mips/cpu.h index 81d1a830..a59b560e 100644 --- a/qemu/target-mips/cpu.h +++ b/qemu/target-mips/cpu.h @@ -1007,7 +1007,12 @@ static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) if (env->insn_flags & ISA_MIPS32R6) { bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; - +#if defined(TARGET_MIPS64) + uint32_t ksux = (1 << CP0St_KX) & val; + ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ + ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ + val = (val & ~(7 << CP0St_UX)) | ksux; +#endif if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { mask &= ~(3 << CP0St_KSU); }