From b41364fdc5f19f4160a31d5d377e0ffec17894ef Mon Sep 17 00:00:00 2001 From: Wanpeng Li Date: Tue, 4 Jun 2019 13:17:31 -0400 Subject: [PATCH] i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor The CPUID.01H:ECX[bit 3] ought to mirror the value of the MSR IA32_MISC_ENABLE MWAIT bit and as userspace has control of them both, it is userspace's job to configure both bits to match on the initial setup. Backports commit 4cfd7bab3f5564f6c1a23b06f73d5aa2f957cd16 from qemu --- qemu/target/i386/cpu.c | 3 +++ qemu/target/i386/cpu.h | 1 + 2 files changed, 4 insertions(+) diff --git a/qemu/target/i386/cpu.c b/qemu/target/i386/cpu.c index b1d9783a..3e9aba20 100644 --- a/qemu/target/i386/cpu.c +++ b/qemu/target/i386/cpu.c @@ -4241,6 +4241,9 @@ static void x86_cpu_reset(CPUState *s) env->pat = 0x0007040600070406ULL; env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; + if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { + env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; + } memset(env->dr, 0, sizeof(env->dr)); env->dr[6] = DR6_FIXED_1; diff --git a/qemu/target/i386/cpu.h b/qemu/target/i386/cpu.h index c15dc465..d28c721b 100644 --- a/qemu/target/i386/cpu.h +++ b/qemu/target/i386/cpu.h @@ -365,6 +365,7 @@ #define MSR_IA32_MISC_ENABLE 0x1a0 /* Indicates good rep/movs microcode on some processors: */ #define MSR_IA32_MISC_ENABLE_DEFAULT 1 +#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)