From b1e52b7958b60a77cc6fdce84ba01ca221957b6e Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Mon, 8 Mar 2021 12:13:56 -0500 Subject: [PATCH] target/riscv: fix vill bit index in vtype register vill bit is at vtype[XLEN-1]. Backports fbcbafa2c1c33ae6630e7717f7f4141befb5b31a --- qemu/target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h index ea3ede80..921318fa 100644 --- a/qemu/target/riscv/cpu.h +++ b/qemu/target/riscv/cpu.h @@ -103,7 +103,7 @@ FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VEDIV, 5, 2) FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1) +FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) struct CPURISCVState { target_ulong gpr[32];