From b117df18dfc93d4ba58fe97e8dc868a11ef8c24c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 8 Mar 2018 22:45:28 -0500 Subject: [PATCH] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 Backports commit c625ff95070e3ef96bd007de744e1d97c881efeb from qemu --- qemu/target/arm/translate-a64.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 0e2fab21..445eb678 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -11544,6 +11544,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ need_fpst = false; break; + case 0x7d: /* FRSQRTE */ case 0x7f: /* FSQRT (vector) */ break; default: @@ -11607,6 +11608,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_ctx, tcg_res, tcg_op, 0x8000); break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus); + break; default: g_assert_not_reached(); } @@ -11659,6 +11663,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_ctx, tcg_res, tcg_op, 0x8000); break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus); + break; case 0x7f: /* FSQRT */ gen_helper_sqrt_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus); break;