From ae94fb5992661c1a05e6ee5d2d00a00592e5ac5b Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Wed, 12 Jun 2019 11:08:38 -0400
Subject: [PATCH] cpu: Define ArchCPU

For all targets, do this just before including exec/cpu-all.h.

Backports commit 2161a612b4e1d388046320bc464adefd6bba01a0 from qemu
---
 qemu/target/arm/cpu.h   | 1 +
 qemu/target/i386/cpu.h  | 1 +
 qemu/target/m68k/cpu.h  | 1 +
 qemu/target/mips/cpu.h  | 1 +
 qemu/target/riscv/cpu.h | 1 +
 qemu/target/sparc/cpu.h | 1 +
 6 files changed, 6 insertions(+)

diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h
index 7b3ef787..79c9e346 100644
--- a/qemu/target/arm/cpu.h
+++ b/qemu/target/arm/cpu.h
@@ -3080,6 +3080,7 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
 }
 
 typedef CPUARMState CPUArchState;
+typedef ARMCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 
diff --git a/qemu/target/i386/cpu.h b/qemu/target/i386/cpu.h
index c84575ea..45ec9cb9 100644
--- a/qemu/target/i386/cpu.h
+++ b/qemu/target/i386/cpu.h
@@ -1671,6 +1671,7 @@ static inline target_long lshift(target_long x, int n)
 void tcg_x86_init(struct uc_struct *);
 
 typedef CPUX86State CPUArchState;
+typedef X86CPU ArchCPU;
 
 #include "exec/cpu-all.h"
 #include "svm.h"
diff --git a/qemu/target/m68k/cpu.h b/qemu/target/m68k/cpu.h
index e7396b30..cc479a48 100644
--- a/qemu/target/m68k/cpu.h
+++ b/qemu/target/m68k/cpu.h
@@ -532,6 +532,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
                                  MemTxResult response, uintptr_t retaddr);
 
 typedef CPUM68KState CPUArchState;
+typedef M68kCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 
diff --git a/qemu/target/mips/cpu.h b/qemu/target/mips/cpu.h
index dd42f5be..552fd057 100644
--- a/qemu/target/mips/cpu.h
+++ b/qemu/target/mips/cpu.h
@@ -1113,6 +1113,7 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
 }
 
 typedef CPUMIPSState CPUArchState;
+typedef MIPSCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 
diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h
index a8e1726f..a624cb56 100644
--- a/qemu/target/riscv/cpu.h
+++ b/qemu/target/riscv/cpu.h
@@ -330,6 +330,7 @@ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 typedef CPURISCVState CPUArchState;
+typedef RISCVCPU ArchCPU;
 
 #include "exec/cpu-all.h"
 
diff --git a/qemu/target/sparc/cpu.h b/qemu/target/sparc/cpu.h
index 64e185fa..771758b4 100644
--- a/qemu/target/sparc/cpu.h
+++ b/qemu/target/sparc/cpu.h
@@ -719,6 +719,7 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
 }
 
 typedef CPUSPARCState CPUArchState;
+typedef SPARCCPU ArchCPU;
 
 #include "exec/cpu-all.h"