diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 7b10fdf8..c8660d5a 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -6410,6 +6410,38 @@ riscv_symbols = ( 'helper_vsra_vx_h', 'helper_vsra_vx_w', 'helper_vsra_vx_d', + 'helper_vminu_vv_b', + 'helper_vminu_vv_h', + 'helper_vminu_vv_w', + 'helper_vminu_vv_d', + 'helper_vmin_vv_b', + 'helper_vmin_vv_h', + 'helper_vmin_vv_w', + 'helper_vmin_vv_d', + 'helper_vmaxu_vv_b', + 'helper_vmaxu_vv_h', + 'helper_vmaxu_vv_w', + 'helper_vmaxu_vv_d', + 'helper_vmax_vv_b', + 'helper_vmax_vv_h', + 'helper_vmax_vv_w', + 'helper_vmax_vv_d', + 'helper_vminu_vx_b', + 'helper_vminu_vx_h', + 'helper_vminu_vx_w', + 'helper_vminu_vx_d', + 'helper_vmin_vx_b', + 'helper_vmin_vx_h', + 'helper_vmin_vx_w', + 'helper_vmin_vx_d', + 'helper_vmaxu_vx_b', + 'helper_vmaxu_vx_h', + 'helper_vmaxu_vx_w', + 'helper_vmaxu_vx_d', + 'helper_vmax_vx_b', + 'helper_vmax_vx_h', + 'helper_vmax_vx_w', + 'helper_vmax_vx_d', 'helper_vmseq_vv_b', 'helper_vmseq_vv_h', 'helper_vmseq_vv_w', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 38374863..9730c0c7 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -3864,6 +3864,94 @@ #define helper_vsra_vx_h helper_vsra_vx_h_riscv32 #define helper_vsra_vx_w helper_vsra_vx_w_riscv32 #define helper_vsra_vx_d helper_vsra_vx_d_riscv32 +#define helper_vminu_vv_b helper_vminu_vv_b_riscv32 +#define helper_vminu_vv_h helper_vminu_vv_h_riscv32 +#define helper_vminu_vv_w helper_vminu_vv_w_riscv32 +#define helper_vminu_vv_d helper_vminu_vv_d_riscv32 +#define helper_vmin_vv_b helper_vmin_vv_b_riscv32 +#define helper_vmin_vv_h helper_vmin_vv_h_riscv32 +#define helper_vmin_vv_w helper_vmin_vv_w_riscv32 +#define helper_vmin_vv_d helper_vmin_vv_d_riscv32 +#define helper_vmaxu_vv_b helper_vmaxu_vv_b_riscv32 +#define helper_vmaxu_vv_h helper_vmaxu_vv_h_riscv32 +#define helper_vmaxu_vv_w helper_vmaxu_vv_w_riscv32 +#define helper_vmaxu_vv_d helper_vmaxu_vv_d_riscv32 +#define helper_vmax_vv_b helper_vmax_vv_b_riscv32 +#define helper_vmax_vv_h helper_vmax_vv_h_riscv32 +#define helper_vmax_vv_w helper_vmax_vv_w_riscv32 +#define helper_vmax_vv_d helper_vmax_vv_d_riscv32 +#define helper_vminu_vx_b helper_vminu_vx_b_riscv32 +#define helper_vminu_vx_h helper_vminu_vx_h_riscv32 +#define helper_vminu_vx_w helper_vminu_vx_w_riscv32 +#define helper_vminu_vx_d helper_vminu_vx_d_riscv32 +#define helper_vmin_vx_b helper_vmin_vx_b_riscv32 +#define helper_vmin_vx_h helper_vmin_vx_h_riscv32 +#define helper_vmin_vx_w helper_vmin_vx_w_riscv32 +#define helper_vmin_vx_d helper_vmin_vx_d_riscv32 +#define helper_vmaxu_vx_b helper_vmaxu_vx_b_riscv32 +#define helper_vmaxu_vx_h helper_vmaxu_vx_h_riscv32 +#define helper_vmaxu_vx_w helper_vmaxu_vx_w_riscv32 +#define helper_vmaxu_vx_d helper_vmaxu_vx_d_riscv32 +#define helper_vmax_vx_b helper_vmax_vx_b_riscv32 +#define helper_vmax_vx_h helper_vmax_vx_h_riscv32 +#define helper_vmax_vx_w helper_vmax_vx_w_riscv32 +#define helper_vmax_vx_d helper_vmax_vx_d_riscv32 +#define helper_vmseq_vv_b helper_vmseq_vv_b_riscv32 +#define helper_vmseq_vv_h helper_vmseq_vv_h_riscv32 +#define helper_vmseq_vv_w helper_vmseq_vv_w_riscv32 +#define helper_vmseq_vv_d helper_vmseq_vv_d_riscv32 +#define helper_vmsne_vv_b helper_vmsne_vv_b_riscv32 +#define helper_vmsne_vv_h helper_vmsne_vv_h_riscv32 +#define helper_vmsne_vv_w helper_vmsne_vv_w_riscv32 +#define helper_vmsne_vv_d helper_vmsne_vv_d_riscv32 +#define helper_vmsltu_vv_b helper_vmsltu_vv_b_riscv32 +#define helper_vmsltu_vv_h helper_vmsltu_vv_h_riscv32 +#define helper_vmsltu_vv_w helper_vmsltu_vv_w_riscv32 +#define helper_vmsltu_vv_d helper_vmsltu_vv_d_riscv32 +#define helper_vmslt_vv_b helper_vmslt_vv_b_riscv32 +#define helper_vmslt_vv_h helper_vmslt_vv_h_riscv32 +#define helper_vmslt_vv_w helper_vmslt_vv_w_riscv32 +#define helper_vmslt_vv_d helper_vmslt_vv_d_riscv32 +#define helper_vmsleu_vv_b helper_vmsleu_vv_b_riscv32 +#define helper_vmsleu_vv_h helper_vmsleu_vv_h_riscv32 +#define helper_vmsleu_vv_w helper_vmsleu_vv_w_riscv32 +#define helper_vmsleu_vv_d helper_vmsleu_vv_d_riscv32 +#define helper_vmsle_vv_b helper_vmsle_vv_b_riscv32 +#define helper_vmsle_vv_h helper_vmsle_vv_h_riscv32 +#define helper_vmsle_vv_w helper_vmsle_vv_w_riscv32 +#define helper_vmsle_vv_d helper_vmsle_vv_d_riscv32 +#define helper_vmseq_vx_b helper_vmseq_vx_b_riscv32 +#define helper_vmseq_vx_h helper_vmseq_vx_h_riscv32 +#define helper_vmseq_vx_w helper_vmseq_vx_w_riscv32 +#define helper_vmseq_vx_d helper_vmseq_vx_d_riscv32 +#define helper_vmsne_vx_b helper_vmsne_vx_b_riscv32 +#define helper_vmsne_vx_h helper_vmsne_vx_h_riscv32 +#define helper_vmsne_vx_w helper_vmsne_vx_w_riscv32 +#define helper_vmsne_vx_d helper_vmsne_vx_d_riscv32 +#define helper_vmsltu_vx_b helper_vmsltu_vx_b_riscv32 +#define helper_vmsltu_vx_h helper_vmsltu_vx_h_riscv32 +#define helper_vmsltu_vx_w helper_vmsltu_vx_w_riscv32 +#define helper_vmsltu_vx_d helper_vmsltu_vx_d_riscv32 +#define helper_vmslt_vx_b helper_vmslt_vx_b_riscv32 +#define helper_vmslt_vx_h helper_vmslt_vx_h_riscv32 +#define helper_vmslt_vx_w helper_vmslt_vx_w_riscv32 +#define helper_vmslt_vx_d helper_vmslt_vx_d_riscv32 +#define helper_vmsleu_vx_b helper_vmsleu_vx_b_riscv32 +#define helper_vmsleu_vx_h helper_vmsleu_vx_h_riscv32 +#define helper_vmsleu_vx_w helper_vmsleu_vx_w_riscv32 +#define helper_vmsleu_vx_d helper_vmsleu_vx_d_riscv32 +#define helper_vmsle_vx_b helper_vmsle_vx_b_riscv32 +#define helper_vmsle_vx_h helper_vmsle_vx_h_riscv32 +#define helper_vmsle_vx_w helper_vmsle_vx_w_riscv32 +#define helper_vmsle_vx_d helper_vmsle_vx_d_riscv32 +#define helper_vmsgtu_vx_b helper_vmsgtu_vx_b_riscv32 +#define helper_vmsgtu_vx_h helper_vmsgtu_vx_h_riscv32 +#define helper_vmsgtu_vx_w helper_vmsgtu_vx_w_riscv32 +#define helper_vmsgtu_vx_d helper_vmsgtu_vx_d_riscv32 +#define helper_vmsgt_vx_b helper_vmsgt_vx_b_riscv32 +#define helper_vmsgt_vx_h helper_vmsgt_vx_h_riscv32 +#define helper_vmsgt_vx_w helper_vmsgt_vx_w_riscv32 +#define helper_vmsgt_vx_d helper_vmsgt_vx_d_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 3d77b105..e3bd5600 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -3864,6 +3864,94 @@ #define helper_vsra_vx_h helper_vsra_vx_h_riscv64 #define helper_vsra_vx_w helper_vsra_vx_w_riscv64 #define helper_vsra_vx_d helper_vsra_vx_d_riscv64 +#define helper_vminu_vv_b helper_vminu_vv_b_riscv64 +#define helper_vminu_vv_h helper_vminu_vv_h_riscv64 +#define helper_vminu_vv_w helper_vminu_vv_w_riscv64 +#define helper_vminu_vv_d helper_vminu_vv_d_riscv64 +#define helper_vmin_vv_b helper_vmin_vv_b_riscv64 +#define helper_vmin_vv_h helper_vmin_vv_h_riscv64 +#define helper_vmin_vv_w helper_vmin_vv_w_riscv64 +#define helper_vmin_vv_d helper_vmin_vv_d_riscv64 +#define helper_vmaxu_vv_b helper_vmaxu_vv_b_riscv64 +#define helper_vmaxu_vv_h helper_vmaxu_vv_h_riscv64 +#define helper_vmaxu_vv_w helper_vmaxu_vv_w_riscv64 +#define helper_vmaxu_vv_d helper_vmaxu_vv_d_riscv64 +#define helper_vmax_vv_b helper_vmax_vv_b_riscv64 +#define helper_vmax_vv_h helper_vmax_vv_h_riscv64 +#define helper_vmax_vv_w helper_vmax_vv_w_riscv64 +#define helper_vmax_vv_d helper_vmax_vv_d_riscv64 +#define helper_vminu_vx_b helper_vminu_vx_b_riscv64 +#define helper_vminu_vx_h helper_vminu_vx_h_riscv64 +#define helper_vminu_vx_w helper_vminu_vx_w_riscv64 +#define helper_vminu_vx_d helper_vminu_vx_d_riscv64 +#define helper_vmin_vx_b helper_vmin_vx_b_riscv64 +#define helper_vmin_vx_h helper_vmin_vx_h_riscv64 +#define helper_vmin_vx_w helper_vmin_vx_w_riscv64 +#define helper_vmin_vx_d helper_vmin_vx_d_riscv64 +#define helper_vmaxu_vx_b helper_vmaxu_vx_b_riscv64 +#define helper_vmaxu_vx_h helper_vmaxu_vx_h_riscv64 +#define helper_vmaxu_vx_w helper_vmaxu_vx_w_riscv64 +#define helper_vmaxu_vx_d helper_vmaxu_vx_d_riscv64 +#define helper_vmax_vx_b helper_vmax_vx_b_riscv64 +#define helper_vmax_vx_h helper_vmax_vx_h_riscv64 +#define helper_vmax_vx_w helper_vmax_vx_w_riscv64 +#define helper_vmax_vx_d helper_vmax_vx_d_riscv64 +#define helper_vmseq_vv_b helper_vmseq_vv_b_riscv64 +#define helper_vmseq_vv_h helper_vmseq_vv_h_riscv64 +#define helper_vmseq_vv_w helper_vmseq_vv_w_riscv64 +#define helper_vmseq_vv_d helper_vmseq_vv_d_riscv64 +#define helper_vmsne_vv_b helper_vmsne_vv_b_riscv64 +#define helper_vmsne_vv_h helper_vmsne_vv_h_riscv64 +#define helper_vmsne_vv_w helper_vmsne_vv_w_riscv64 +#define helper_vmsne_vv_d helper_vmsne_vv_d_riscv64 +#define helper_vmsltu_vv_b helper_vmsltu_vv_b_riscv64 +#define helper_vmsltu_vv_h helper_vmsltu_vv_h_riscv64 +#define helper_vmsltu_vv_w helper_vmsltu_vv_w_riscv64 +#define helper_vmsltu_vv_d helper_vmsltu_vv_d_riscv64 +#define helper_vmslt_vv_b helper_vmslt_vv_b_riscv64 +#define helper_vmslt_vv_h helper_vmslt_vv_h_riscv64 +#define helper_vmslt_vv_w helper_vmslt_vv_w_riscv64 +#define helper_vmslt_vv_d helper_vmslt_vv_d_riscv64 +#define helper_vmsleu_vv_b helper_vmsleu_vv_b_riscv64 +#define helper_vmsleu_vv_h helper_vmsleu_vv_h_riscv64 +#define helper_vmsleu_vv_w helper_vmsleu_vv_w_riscv64 +#define helper_vmsleu_vv_d helper_vmsleu_vv_d_riscv64 +#define helper_vmsle_vv_b helper_vmsle_vv_b_riscv64 +#define helper_vmsle_vv_h helper_vmsle_vv_h_riscv64 +#define helper_vmsle_vv_w helper_vmsle_vv_w_riscv64 +#define helper_vmsle_vv_d helper_vmsle_vv_d_riscv64 +#define helper_vmseq_vx_b helper_vmseq_vx_b_riscv64 +#define helper_vmseq_vx_h helper_vmseq_vx_h_riscv64 +#define helper_vmseq_vx_w helper_vmseq_vx_w_riscv64 +#define helper_vmseq_vx_d helper_vmseq_vx_d_riscv64 +#define helper_vmsne_vx_b helper_vmsne_vx_b_riscv64 +#define helper_vmsne_vx_h helper_vmsne_vx_h_riscv64 +#define helper_vmsne_vx_w helper_vmsne_vx_w_riscv64 +#define helper_vmsne_vx_d helper_vmsne_vx_d_riscv64 +#define helper_vmsltu_vx_b helper_vmsltu_vx_b_riscv64 +#define helper_vmsltu_vx_h helper_vmsltu_vx_h_riscv64 +#define helper_vmsltu_vx_w helper_vmsltu_vx_w_riscv64 +#define helper_vmsltu_vx_d helper_vmsltu_vx_d_riscv64 +#define helper_vmslt_vx_b helper_vmslt_vx_b_riscv64 +#define helper_vmslt_vx_h helper_vmslt_vx_h_riscv64 +#define helper_vmslt_vx_w helper_vmslt_vx_w_riscv64 +#define helper_vmslt_vx_d helper_vmslt_vx_d_riscv64 +#define helper_vmsleu_vx_b helper_vmsleu_vx_b_riscv64 +#define helper_vmsleu_vx_h helper_vmsleu_vx_h_riscv64 +#define helper_vmsleu_vx_w helper_vmsleu_vx_w_riscv64 +#define helper_vmsleu_vx_d helper_vmsleu_vx_d_riscv64 +#define helper_vmsle_vx_b helper_vmsle_vx_b_riscv64 +#define helper_vmsle_vx_h helper_vmsle_vx_h_riscv64 +#define helper_vmsle_vx_w helper_vmsle_vx_w_riscv64 +#define helper_vmsle_vx_d helper_vmsle_vx_d_riscv64 +#define helper_vmsgtu_vx_b helper_vmsgtu_vx_b_riscv64 +#define helper_vmsgtu_vx_h helper_vmsgtu_vx_h_riscv64 +#define helper_vmsgtu_vx_w helper_vmsgtu_vx_w_riscv64 +#define helper_vmsgtu_vx_d helper_vmsgtu_vx_d_riscv64 +#define helper_vmsgt_vx_b helper_vmsgt_vx_b_riscv64 +#define helper_vmsgt_vx_h helper_vmsgt_vx_h_riscv64 +#define helper_vmsgt_vx_w helper_vmsgt_vx_w_riscv64 +#define helper_vmsgt_vx_d helper_vmsgt_vx_d_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index f6416df0..45b9047b 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -492,3 +492,36 @@ DEF_HELPER_6(vmsgt_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsgt_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsgt_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmsgt_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vminu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vminu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vminu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vminu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmin_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmaxu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmaxu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmaxu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmaxu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmax_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmax_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmax_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmax_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vminu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vminu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vminu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vminu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmin_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmin_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmin_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmin_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmaxu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmaxu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmaxu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmaxu_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmax_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmax_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmax_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmax_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index ba12d8be..30366c65 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -351,6 +351,14 @@ vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm +vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm +vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm +vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm +vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm +vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm +vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm +vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm +vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index abf64c31..fa7bc1b4 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -1492,3 +1492,13 @@ GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check) + +/* Vector Integer Min/Max Instructions */ +GEN_OPIVV_GVEC_TRANS(vminu_vv, umin) +GEN_OPIVV_GVEC_TRANS(vmin_vv, smin) +GEN_OPIVV_GVEC_TRANS(vmaxu_vv, umax) +GEN_OPIVV_GVEC_TRANS(vmax_vv, smax) +GEN_OPIVX_TRANS(vminu_vx, opivx_check) +GEN_OPIVX_TRANS(vmin_vx, opivx_check) +GEN_OPIVX_TRANS(vmaxu_vx, opivx_check) +GEN_OPIVX_TRANS(vmax_vx, opivx_check) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index c6ca7154..d453414e 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -856,6 +856,10 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl) #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t +#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t +#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t +#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t +#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t /* operation of two vector elements */ typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); @@ -1519,3 +1523,70 @@ GEN_VEXT_CMP_VX(vmsgt_vx_b, int8_t, H1, DO_MSGT) GEN_VEXT_CMP_VX(vmsgt_vx_h, int16_t, H2, DO_MSGT) GEN_VEXT_CMP_VX(vmsgt_vx_w, int32_t, H4, DO_MSGT) GEN_VEXT_CMP_VX(vmsgt_vx_d, int64_t, H8, DO_MSGT) + +/* Vector Integer Min/Max Instructions */ +RVVCALL(OPIVV2, vminu_vv_b, OP_UUU_B, H1, H1, H1, DO_MIN) +RVVCALL(OPIVV2, vminu_vv_h, OP_UUU_H, H2, H2, H2, DO_MIN) +RVVCALL(OPIVV2, vminu_vv_w, OP_UUU_W, H4, H4, H4, DO_MIN) +RVVCALL(OPIVV2, vminu_vv_d, OP_UUU_D, H8, H8, H8, DO_MIN) +RVVCALL(OPIVV2, vmin_vv_b, OP_SSS_B, H1, H1, H1, DO_MIN) +RVVCALL(OPIVV2, vmin_vv_h, OP_SSS_H, H2, H2, H2, DO_MIN) +RVVCALL(OPIVV2, vmin_vv_w, OP_SSS_W, H4, H4, H4, DO_MIN) +RVVCALL(OPIVV2, vmin_vv_d, OP_SSS_D, H8, H8, H8, DO_MIN) +RVVCALL(OPIVV2, vmaxu_vv_b, OP_UUU_B, H1, H1, H1, DO_MAX) +RVVCALL(OPIVV2, vmaxu_vv_h, OP_UUU_H, H2, H2, H2, DO_MAX) +RVVCALL(OPIVV2, vmaxu_vv_w, OP_UUU_W, H4, H4, H4, DO_MAX) +RVVCALL(OPIVV2, vmaxu_vv_d, OP_UUU_D, H8, H8, H8, DO_MAX) +RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX) +RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX) +RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX) +RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX) +GEN_VEXT_VV(vminu_vv_b, 1, 1, clearb) +GEN_VEXT_VV(vminu_vv_h, 2, 2, clearh) +GEN_VEXT_VV(vminu_vv_w, 4, 4, clearl) +GEN_VEXT_VV(vminu_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vmin_vv_b, 1, 1, clearb) +GEN_VEXT_VV(vmin_vv_h, 2, 2, clearh) +GEN_VEXT_VV(vmin_vv_w, 4, 4, clearl) +GEN_VEXT_VV(vmin_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vmaxu_vv_b, 1, 1, clearb) +GEN_VEXT_VV(vmaxu_vv_h, 2, 2, clearh) +GEN_VEXT_VV(vmaxu_vv_w, 4, 4, clearl) +GEN_VEXT_VV(vmaxu_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vmax_vv_b, 1, 1, clearb) +GEN_VEXT_VV(vmax_vv_h, 2, 2, clearh) +GEN_VEXT_VV(vmax_vv_w, 4, 4, clearl) +GEN_VEXT_VV(vmax_vv_d, 8, 8, clearq) + +RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN) +RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN) +RVVCALL(OPIVX2, vminu_vx_w, OP_UUU_W, H4, H4, DO_MIN) +RVVCALL(OPIVX2, vminu_vx_d, OP_UUU_D, H8, H8, DO_MIN) +RVVCALL(OPIVX2, vmin_vx_b, OP_SSS_B, H1, H1, DO_MIN) +RVVCALL(OPIVX2, vmin_vx_h, OP_SSS_H, H2, H2, DO_MIN) +RVVCALL(OPIVX2, vmin_vx_w, OP_SSS_W, H4, H4, DO_MIN) +RVVCALL(OPIVX2, vmin_vx_d, OP_SSS_D, H8, H8, DO_MIN) +RVVCALL(OPIVX2, vmaxu_vx_b, OP_UUU_B, H1, H1, DO_MAX) +RVVCALL(OPIVX2, vmaxu_vx_h, OP_UUU_H, H2, H2, DO_MAX) +RVVCALL(OPIVX2, vmaxu_vx_w, OP_UUU_W, H4, H4, DO_MAX) +RVVCALL(OPIVX2, vmaxu_vx_d, OP_UUU_D, H8, H8, DO_MAX) +RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX) +RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX) +RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX) +RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX) +GEN_VEXT_VX(vminu_vx_b, 1, 1, clearb) +GEN_VEXT_VX(vminu_vx_h, 2, 2, clearh) +GEN_VEXT_VX(vminu_vx_w, 4, 4, clearl) +GEN_VEXT_VX(vminu_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vmin_vx_b, 1, 1, clearb) +GEN_VEXT_VX(vmin_vx_h, 2, 2, clearh) +GEN_VEXT_VX(vmin_vx_w, 4, 4, clearl) +GEN_VEXT_VX(vmin_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vmaxu_vx_b, 1, 1, clearb) +GEN_VEXT_VX(vmaxu_vx_h, 2, 2, clearh) +GEN_VEXT_VX(vmaxu_vx_w, 4, 4, clearl) +GEN_VEXT_VX(vmaxu_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vmax_vx_b, 1, 1, clearb) +GEN_VEXT_VX(vmax_vx_h, 2, 2, clearh) +GEN_VEXT_VX(vmax_vx_w, 4, 4, clearl) +GEN_VEXT_VX(vmax_vx_d, 8, 8, clearq)