From a9fb3994904a431f9babe583dc7200acdb0e5a86 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sat, 24 Feb 2018 18:18:14 -0500 Subject: [PATCH] target-arm: Fix reset and migration of TTBCR(S) Commit 6459b94c26dd666badb3 broke reset and migration of the AArch32 TTBCR(S) register if the guest used non-LPAE page tables. This is because the AArch32 TTBCR register definition is marked as ARM_CP_ALIAS, meaning that the AArch64 variant has to handle migration and reset. Although AArch64 TCR_EL3 doesn't need to care about the mask and base_mask fields, AArch32 may do so, and so we must use the special TTBCR reset and raw write functions to ensure they are set correctly. This doesn't affect TCR_EL2, because the AArch32 equivalent of that is HTCR, which never uses the non-LPAE page table variant. Backports commit 811595a2d4ab8c6354857a50ffd29fafce52a892 from qemu --- qemu/target-arm/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index 290a3569..53a690db 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -3278,9 +3278,11 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { { "TCR_EL3", 0,2,0, 3,6,2, ARM_CP_STATE_AA64,0, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tcr_el[3]), {0, 0}, /* no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask + * we must provide a .raw_writefn and .resetfn because we handle + * reset and migration for the AArch32 TTBCR(S), which might be + * using mask and base_mask. */ - NULL, NULL, NULL, NULL, NULL, NULL }, + NULL, NULL, NULL, NULL, vmsa_ttbcr_raw_write, vmsa_ttbcr_reset }, { "ELR_EL3", 0,4,0, 3,6,1, ARM_CP_STATE_AA64, ARM_CP_ALIAS, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[3]) }, { "ESR_EL3", 0,5,2, 3,6,0, ARM_CP_STATE_AA64, 0,