diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 005dbf69..fd12c017 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -4935,6 +4935,7 @@ mips_symbols = (
     'helper_mtc0_pagemask',
     'helper_mtc0_performance0',
     'helper_mtc0_pwfield',
+    'helper_mtc0_pwsize',
     'helper_mtc0_segctl0',
     'helper_mtc0_segctl1',
     'helper_mtc0_segctl2',
diff --git a/qemu/mips.h b/qemu/mips.h
index f1409661..aba177e2 100644
--- a/qemu/mips.h
+++ b/qemu/mips.h
@@ -3909,6 +3909,7 @@
 #define helper_mtc0_pagemask helper_mtc0_pagemask_mips
 #define helper_mtc0_performance0 helper_mtc0_performance0_mips
 #define helper_mtc0_pwfield helper_mtc0_pwfield_mips
+#define helper_mtc0_pwsize helper_mtc0_pwsize_mips
 #define helper_mtc0_segctl0 helper_mtc0_segctl0_mips
 #define helper_mtc0_segctl1 helper_mtc0_segctl1_mips
 #define helper_mtc0_segctl2 helper_mtc0_segctl2_mips
diff --git a/qemu/mips64.h b/qemu/mips64.h
index ccd4718e..1885c7a2 100644
--- a/qemu/mips64.h
+++ b/qemu/mips64.h
@@ -3909,6 +3909,7 @@
 #define helper_mtc0_pagemask helper_mtc0_pagemask_mips64
 #define helper_mtc0_performance0 helper_mtc0_performance0_mips64
 #define helper_mtc0_pwfield helper_mtc0_pwfield_mips64
+#define helper_mtc0_pwsize helper_mtc0_pwsize_mips64
 #define helper_mtc0_segctl0 helper_mtc0_segctl0_mips64
 #define helper_mtc0_segctl1 helper_mtc0_segctl1_mips64
 #define helper_mtc0_segctl2 helper_mtc0_segctl2_mips64
diff --git a/qemu/mips64el.h b/qemu/mips64el.h
index e769fefd..8905ca22 100644
--- a/qemu/mips64el.h
+++ b/qemu/mips64el.h
@@ -3909,6 +3909,7 @@
 #define helper_mtc0_pagemask helper_mtc0_pagemask_mips64el
 #define helper_mtc0_performance0 helper_mtc0_performance0_mips64el
 #define helper_mtc0_pwfield helper_mtc0_pwfield_mips64el
+#define helper_mtc0_pwsize helper_mtc0_pwsize_mips64el
 #define helper_mtc0_segctl0 helper_mtc0_segctl0_mips64el
 #define helper_mtc0_segctl1 helper_mtc0_segctl1_mips64el
 #define helper_mtc0_segctl2 helper_mtc0_segctl2_mips64el
diff --git a/qemu/mipsel.h b/qemu/mipsel.h
index 1359db5d..28550a90 100644
--- a/qemu/mipsel.h
+++ b/qemu/mipsel.h
@@ -3909,6 +3909,7 @@
 #define helper_mtc0_pagemask helper_mtc0_pagemask_mipsel
 #define helper_mtc0_performance0 helper_mtc0_performance0_mipsel
 #define helper_mtc0_pwfield helper_mtc0_pwfield_mipsel
+#define helper_mtc0_pwsize helper_mtc0_pwsize_mipsel
 #define helper_mtc0_segctl0 helper_mtc0_segctl0_mipsel
 #define helper_mtc0_segctl1 helper_mtc0_segctl1_mipsel
 #define helper_mtc0_segctl2 helper_mtc0_segctl2_mipsel
diff --git a/qemu/target/mips/cpu.h b/qemu/target/mips/cpu.h
index 2b66814c..35faeb08 100644
--- a/qemu/target/mips/cpu.h
+++ b/qemu/target/mips/cpu.h
@@ -433,6 +433,16 @@ struct CPUMIPSState {
 #define CP0PF_PTW  6     /* 11..6  */
 #define CP0PF_PTEW 0     /*  5..0  */
 #endif
+    target_ulong CP0_PWSize;
+#if defined(TARGET_MIPS64)
+#define CP0PS_BDW  32    /* 37..32 */
+#endif
+#define CP0PS_PS   30
+#define CP0PS_GDW  24    /* 29..24 */
+#define CP0PS_UDW  18    /* 23..18 */
+#define CP0PS_MDW  12    /* 17..12 */
+#define CP0PS_PTW  6     /* 11..6  */
+#define CP0PS_PTEW 0     /*  5..0  */
 /*
  * CP0 Register 6
  */
diff --git a/qemu/target/mips/helper.h b/qemu/target/mips/helper.h
index f906f0da..6152de36 100644
--- a/qemu/target/mips/helper.h
+++ b/qemu/target/mips/helper.h
@@ -121,6 +121,7 @@ DEF_HELPER_2(mtc0_segctl0, void, env, tl)
 DEF_HELPER_2(mtc0_segctl1, void, env, tl)
 DEF_HELPER_2(mtc0_segctl2, void, env, tl)
 DEF_HELPER_2(mtc0_pwfield, void, env, tl)
+DEF_HELPER_2(mtc0_pwsize, void, env, tl)
 DEF_HELPER_2(mtc0_wired, void, env, tl)
 DEF_HELPER_2(mtc0_srsconf0, void, env, tl)
 DEF_HELPER_2(mtc0_srsconf1, void, env, tl)
diff --git a/qemu/target/mips/op_helper.c b/qemu/target/mips/op_helper.c
index 6a09a0f3..08ea5408 100644
--- a/qemu/target/mips/op_helper.c
+++ b/qemu/target/mips/op_helper.c
@@ -1497,6 +1497,15 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
 #endif
 }
 
+void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
+{
+#if defined(TARGET_MIPS64)
+    env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
+#else
+    env->CP0_PWSize = arg1 & 0x3FFFFFFF;
+#endif
+}
+
 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
 {
     if (env->insn_flags & ISA_MIPS32R6) {
diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c
index bcccfe10..3dcd9dbe 100644
--- a/qemu/target/mips/translate.c
+++ b/qemu/target/mips/translate.c
@@ -6200,6 +6200,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PWField));
             rn = "PWField";
             break;
+        case 7:
+            check_pw(ctx);
+            gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PWSize));
+            rn = "PWSize";
+            break;
         default:
             goto cp0_unimplemented;
         }
@@ -6907,6 +6912,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             gen_helper_mtc0_pwfield(tcg_ctx, tcg_ctx->cpu_env, arg);
             rn = "PWField";
             break;
+        case 7:
+            check_pw(ctx);
+            gen_helper_mtc0_pwsize(tcg_ctx, tcg_ctx->cpu_env, arg);
+            rn = "PWSize";
+            break;
         default:
             goto cp0_unimplemented;
         }
@@ -7624,6 +7634,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_PWField));
             rn = "PWField";
             break;
+        case 7:
+            check_pw(ctx);
+            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
+            rn = "PWSize";
+            break;
         default:
             goto cp0_unimplemented;
         }
@@ -8313,6 +8328,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             gen_helper_mtc0_pwfield(tcg_ctx, tcg_ctx->cpu_env, arg);
             rn = "PWField";
             break;
+        case 7:
+            check_pw(ctx);
+            gen_helper_mtc0_pwsize(tcg_ctx, tcg_ctx->cpu_env, arg);
+            rn = "PWSize";
+            break;
         default:
             goto cp0_unimplemented;
         }