From a47fb718bc7260ffa217260b1c62256eb89cbe65 Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Wed, 7 Mar 2018 11:34:52 -0500
Subject: [PATCH] target/arm: Add predicate registers for SVE

Backports commit 3c7d30866fd1f56e5945726221410e0d8d535033 from qemu
---
 qemu/target/arm/cpu.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h
index 6c9be9bf..aa562104 100644
--- a/qemu/target/arm/cpu.h
+++ b/qemu/target/arm/cpu.h
@@ -193,6 +193,13 @@ typedef struct ARMVectorReg {
     uint64_t QEMU_ALIGNED(16, d[2 * ARM_MAX_VQ]);
 } ARMVectorReg;
 
+/* In AArch32 mode, predicate registers do not exist at all.  */
+#ifdef TARGET_AARCH64
+typedef struct ARMPredicateReg {
+    uint64_t QEMU_ALIGNED(16, p[2 * ARM_MAX_VQ / 8]);
+} ARMPredicateReg;
+#endif
+
 typedef struct CPUARMState {
     /* Regs for current mode.  */
     uint32_t regs[16];
@@ -519,6 +526,11 @@ typedef struct CPUARMState {
     struct {
         ARMVectorReg zregs[32];
 
+#ifdef TARGET_AARCH64
+        /* Store FFR as pregs[16] to make it easier to treat as any other.  */
+        ARMPredicateReg pregs[17];
+#endif
+
         uint32_t xregs[16];
         /* We store these fpcsr fields separately for convenience.  */
         int vec_len;