From a2194585bb46328a93249eb6f07fdc9279cacfcc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jean-Hugues=20Desch=C3=AAnes?= Date: Thu, 28 Nov 2019 03:40:31 -0500 Subject: [PATCH] target/arm: Fix handling of cortex-m FTYPE flag in EXCRET According to the PushStack() pseudocode in the armv7m RM, bit 4 of the LR should be set to NOT(CONTROL.PFCA) when an FPU is present. Current implementation is doing it for armv8, but not for armv7. This patch makes the existing logic applicable to both code paths. Backports commit f900b1e5b087a02199fbb6de7038828008e9e419 from qemu --- qemu/target/arm/m_helper.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/qemu/target/arm/m_helper.c b/qemu/target/arm/m_helper.c index 5edddb68..146bd0e5 100644 --- a/qemu/target/arm/m_helper.c +++ b/qemu/target/arm/m_helper.c @@ -2176,19 +2176,18 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) if (env->v7m.secure) { lr |= R_V7M_EXCRET_S_MASK; } - if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { - lr |= R_V7M_EXCRET_FTYPE_MASK; - } } else { lr = R_V7M_EXCRET_RES1_MASK | R_V7M_EXCRET_S_MASK | R_V7M_EXCRET_DCRS_MASK | - R_V7M_EXCRET_FTYPE_MASK | R_V7M_EXCRET_ES_MASK; if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) { lr |= R_V7M_EXCRET_SPSEL_MASK; } } + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { + lr |= R_V7M_EXCRET_FTYPE_MASK; + } if (!arm_v7m_is_handler_mode(env)) { lr |= R_V7M_EXCRET_MODE_MASK; }