From a011318794a625f2d6873ddb7456f758181c02dd Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 19 Nov 2019 14:13:50 -0500 Subject: [PATCH] target/arm: Simplify op_smlawx for SMLAW* By shifting the 16-bit input left by 16, we can align the desired portion of the 48-bit product and use tcg_gen_muls2_i32. Backports commit 485b607d4f393e0de92c922806a68aef22340c98 from qemu --- qemu/target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index db72ded4..35d69956 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -8464,7 +8464,6 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) { TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 t0, t1; - TCGv_i64 t64; if (!ENABLE_ARCH_5TE) { return false; @@ -8472,16 +8471,17 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) t0 = load_reg(s, a->rn); t1 = load_reg(s, a->rm); + /* + * Since the nominal result is product<47:16>, shift the 16-bit + * input up by 16 bits, so that the result is at product<63:32>. + */ if (mt) { - tcg_gen_sari_i32(tcg_ctx, t1, t1, 16); + tcg_gen_andi_i32(tcg_ctx, t1, t1, 0xffff0000); } else { - gen_sxth(t1); + tcg_gen_shli_i32(tcg_ctx, t1, t1, 16); } - t64 = gen_muls_i64_i32(s, t0, t1); - tcg_gen_shri_i64(tcg_ctx, t64, t64, 16); - t1 = tcg_temp_new_i32(tcg_ctx); - tcg_gen_extrl_i64_i32(tcg_ctx, t1, t64); - tcg_temp_free_i64(tcg_ctx, t64); + tcg_gen_muls2_i32(tcg_ctx, t0, t1, t0, t1); + tcg_temp_free_i32(tcg_ctx, t0); if (add) { t0 = load_reg(s, a->ra); gen_helper_add_setq(tcg_ctx, t1, tcg_ctx->cpu_env, t1, t0);